Re: [Qemu-devel] [PATCH v12 07/14] target-mips: Add ASE DSP GPR-based shift instructions

[Aurelien Jarno]

On Wed, Oct 31, 2012 at 09:26:08PM +0800, Jia Liu wrote:
> Hi Aurelien,
> 
> Is this time OK?

Yes, the explanation is fine, though it means the generated code is then
not really optimal. On the other hand it means the op is doing what it
is supposed to do.

> static void gen_mipsdsp_shift(DisasContext *ctx, uint32_t opc,
>                               int ret, int v1, int v2)
> {
>     uint32_t op2;
>     const char *opn = "mipsdsp shift";
>     TCGv t0;
>     TCGv v1_t;
>     TCGv v2_t;
> 
>     if (ret == 0) {
>         /* Treat as NOP. */
>         MIPS_DEBUG("NOP");
>         return;
>     }
> 
>     if ((v1 < 0 || v1 > 32) || (v2 < 0 || v2 > 32)) {
>         generate_exception(ctx, EXCP_RI);
>         return;
>     }
> 
>     t0 = tcg_temp_new();
>     v1_t = tcg_temp_new();
>     v2_t = tcg_temp_new();
> 
>     tcg_gen_movi_tl(t0, v1);
>     gen_load_gpr(v1_t, v1);
>     gen_load_gpr(v2_t, v2);
> 
>     switch (opc) {
>     case OPC_SHLL_QB_DSP:
>         {
>             op2 = MASK_SHLL_QB(ctx->opcode);
>             switch (op2) {
>             case OPC_SHLL_QB:
>                 check_dsp(ctx);
>                 gen_helper_shll_qb(cpu_gpr[ret], t0, v2_t, cpu_env);
>                 break;
>             case OPC_SHLLV_QB:
>                 check_dsp(ctx);
>                 gen_helper_shll_qb(cpu_gpr[ret], v1_t, v2_t, cpu_env);
>                 break;
>             case OPC_SHLL_PH:
>                 check_dsp(ctx);
>                 gen_helper_shll_ph(cpu_gpr[ret], t0, v2_t, cpu_env);
>                 break;
>             case OPC_SHLLV_PH:
>                 check_dsp(ctx);
>                 gen_helper_shll_ph(cpu_gpr[ret], v1_t, v2_t, cpu_env);
>                 break;
>             case OPC_SHLL_S_PH:
>                 check_dsp(ctx);
>                 gen_helper_shll_s_ph(cpu_gpr[ret], t0, v2_t, cpu_env);
>                 break;
>             case OPC_SHLLV_S_PH:
>                 check_dsp(ctx);
>                 gen_helper_shll_s_ph(cpu_gpr[ret], v1_t, v2_t, cpu_env);
>                 break;
>             case OPC_SHLL_S_W:
>                 check_dsp(ctx);
>                 gen_helper_shll_s_w(cpu_gpr[ret], t0, v2_t, cpu_env);
>                 break;
>             case OPC_SHLLV_S_W:
>                 check_dsp(ctx);
>                 gen_helper_shll_s_w(cpu_gpr[ret], v1_t, v2_t, cpu_env);
>                 break;
>             case OPC_SHRL_QB:
>                 check_dsp(ctx);
>                 gen_helper_shrl_qb(cpu_gpr[ret], t0, v2_t);
>                 break;
>             case OPC_SHRLV_QB:
>                 check_dsp(ctx);
>                 gen_helper_shrl_qb(cpu_gpr[ret], v1_t, v2_t);
>                 break;
>             case OPC_SHRL_PH:
>                 check_dspr2(ctx);
>                 gen_helper_shrl_ph(cpu_gpr[ret], t0, v2_t);
>                 break;
>             case OPC_SHRLV_PH:
>                 check_dspr2(ctx);
>                 gen_helper_shrl_ph(cpu_gpr[ret], v1_t, v2_t);
>                 break;
>             case OPC_SHRA_QB:
>                 check_dspr2(ctx);
>                 gen_helper_shra_qb(cpu_gpr[ret], t0, v2_t);
>                 break;
>             case OPC_SHRA_R_QB:
>                 check_dspr2(ctx);
>                 gen_helper_shra_r_qb(cpu_gpr[ret], t0, v2_t);
>                 break;
>             case OPC_SHRAV_QB:
>                 check_dspr2(ctx);
>                 gen_helper_shra_qb(cpu_gpr[ret], v1_t, v2_t);
>                 break;
>             case OPC_SHRAV_R_QB:
>                 check_dspr2(ctx);
>                 gen_helper_shra_r_qb(cpu_gpr[ret], v1_t, v2_t);
>                 break;
>             case OPC_SHRA_PH:
>                 check_dsp(ctx);
>                 gen_helper_shra_ph(cpu_gpr[ret], t0, v2_t);
>                 break;
>             case OPC_SHRA_R_PH:
>                 check_dsp(ctx);
>                 gen_helper_shra_r_ph(cpu_gpr[ret], t0, v2_t);
>                 break;
>             case OPC_SHRAV_PH:
>                 check_dsp(ctx);
>                 gen_helper_shra_ph(cpu_gpr[ret], v1_t, v2_t);
>                 break;
>             case OPC_SHRAV_R_PH:
>                 check_dsp(ctx);
>                 gen_helper_shra_r_ph(cpu_gpr[ret], v1_t, v2_t);
>                 break;
>             case OPC_SHRA_R_W:
>                 check_dsp(ctx);
>                 gen_helper_shra_r_w(cpu_gpr[ret], t0, v2_t);
>                 break;
>             case OPC_SHRAV_R_W:
>                 check_dsp(ctx);
>                 gen_helper_shra_r_w(cpu_gpr[ret], v1_t, v2_t);
>                 break;
>             default:            /* Invalid */
>                 MIPS_INVAL("MASK SHLL.QB");
>                 generate_exception(ctx, EXCP_RI);
>                 break;
>             }
>             break;
>         }
> #ifdef TARGET_MIPS64
>     case OPC_SHLL_OB_DSP:
>         op2 = MASK_SHLL_OB(ctx->opcode);
>         switch (op2) {
>         case OPC_SHLL_PW:
>             check_dsp(ctx);
>             gen_helper_shll_pw(cpu_gpr[ret], v2_t, t0, cpu_env);
>             break;
>         case OPC_SHLLV_PW:
>             check_dsp(ctx);
>             gen_helper_shll_pw(cpu_gpr[ret], v2_t, v1_t, cpu_env);
>             break;
>         case OPC_SHLL_S_PW:
>             check_dsp(ctx);
>             gen_helper_shll_s_pw(cpu_gpr[ret], v2_t, t0, cpu_env);
>             break;
>         case OPC_SHLLV_S_PW:
>             check_dsp(ctx);
>             gen_helper_shll_s_pw(cpu_gpr[ret], v2_t, v1_t, cpu_env);
>             break;
>         case OPC_SHLL_OB:
>             check_dsp(ctx);
>             gen_helper_shll_ob(cpu_gpr[ret], v2_t, t0, cpu_env);
>             break;
>         case OPC_SHLLV_OB:
>             check_dsp(ctx);
>             gen_helper_shll_ob(cpu_gpr[ret], v2_t, v1_t, cpu_env);
>             break;
>         case OPC_SHLL_QH:
>             check_dsp(ctx);
>             gen_helper_shll_qh(cpu_gpr[ret], v2_t, t0, cpu_env);
>             break;
>         case OPC_SHLLV_QH:
>             check_dsp(ctx);
>             gen_helper_shll_qh(cpu_gpr[ret], v2_t, v1_t, cpu_env);
>             break;
>         case OPC_SHLL_S_QH:
>             check_dsp(ctx);
>             gen_helper_shll_s_qh(cpu_gpr[ret], v2_t, t0, cpu_env);
>             break;
>         case OPC_SHLLV_S_QH:
>             check_dsp(ctx);
>             gen_helper_shll_s_qh(cpu_gpr[ret], v2_t, v1_t, cpu_env);
>             break;
>         case OPC_SHRA_OB:
>             check_dspr2(ctx);
>             gen_helper_shra_ob(cpu_gpr[ret], v2_t, t0);
>             break;
>         case OPC_SHRAV_OB:
>             check_dspr2(ctx);
>             gen_helper_shra_ob(cpu_gpr[ret], v2_t, v1_t);
>             break;
>         case OPC_SHRA_R_OB:
>             check_dspr2(ctx);
>             gen_helper_shra_r_ob(cpu_gpr[ret], v2_t, t0);
>             break;
>         case OPC_SHRAV_R_OB:
>             check_dspr2(ctx);
>             gen_helper_shra_r_ob(cpu_gpr[ret], v2_t, v1_t);
>             break;
>         case OPC_SHRA_PW:
>             check_dsp(ctx);
>             gen_helper_shra_pw(cpu_gpr[ret], v2_t, t0);
>             break;
>         case OPC_SHRAV_PW:
>             check_dsp(ctx);
>             gen_helper_shra_pw(cpu_gpr[ret], v2_t, v1_t);
>             break;
>         case OPC_SHRA_R_PW:
>             check_dsp(ctx);
>             gen_helper_shra_r_pw(cpu_gpr[ret], v2_t, t0);
>             break;
>         case OPC_SHRAV_R_PW:
>             check_dsp(ctx);
>             gen_helper_shra_r_pw(cpu_gpr[ret], v2_t, v1_t);
>             break;
>         case OPC_SHRA_QH:
>             check_dsp(ctx);
>             gen_helper_shra_qh(cpu_gpr[ret], v2_t, t0);
>             break;
>         case OPC_SHRAV_QH:
>             check_dsp(ctx);
>             gen_helper_shra_qh(cpu_gpr[ret], v2_t, v1_t);
>             break;
>         case OPC_SHRA_R_QH:
>             check_dsp(ctx);
>             gen_helper_shra_r_qh(cpu_gpr[ret], v2_t, t0);
>             break;
>         case OPC_SHRAV_R_QH:
>             check_dsp(ctx);
>             gen_helper_shra_r_qh(cpu_gpr[ret], v2_t, v1_t);
>             break;
>         case OPC_SHRL_OB:
>             check_dsp(ctx);
>             gen_helper_shrl_ob(cpu_gpr[ret], v2_t, t0);
>             break;
>         case OPC_SHRLV_OB:
>             check_dsp(ctx);
>             gen_helper_shrl_ob(cpu_gpr[ret], v2_t, v1_t);
>             break;
>         case OPC_SHRL_QH:
>             check_dspr2(ctx);
>             gen_helper_shrl_qh(cpu_gpr[ret], v2_t, t0);
>             break;
>         case OPC_SHRLV_QH:
>             check_dspr2(ctx);
>             gen_helper_shrl_qh(cpu_gpr[ret], v2_t, v1_t);
>             break;
>         default:            /* Invalid */
>             MIPS_INVAL("MASK SHLL.OB");
>             generate_exception(ctx, EXCP_RI);
>             break;
>         }
>         break;
> #endif
>     }
> 
>     tcg_temp_free(t0);
>     tcg_temp_free(v1_t);
>     tcg_temp_free(v2_t);
>     (void)opn; /* avoid a compiler warning */
>     MIPS_DEBUG("%s", opn);
> }
> 
> Regards,
> Jia.
> 

-- 
Aurelien Jarno                          GPG: 1024D/F1BCDB73
address@hidden                 http://www.aurel32.net