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Re: [Qemu-devel] [PATCH v5 5/6] i8259: fix so that dropping IRQ level al
From: |
Maciej W. Rozycki |
Subject: |
Re: [Qemu-devel] [PATCH v5 5/6] i8259: fix so that dropping IRQ level always clears the interrupt request |
Date: |
Mon, 10 Sep 2012 14:09:23 +0100 (BST) |
User-agent: |
Alpine 2.00 (LFD 1167 2008-08-23) |
On Mon, 10 Sep 2012, Avi Kivity wrote:
> >>> So the only difference between edge triggered and level triggered
> >>> is in the leading edge, with no difference in the trailing edge.
> >>
> >> Hard to believe. So an edge while cpu interrupts are disabled is ignored?
Please note that x86 CPU's INT input is level-triggered, not
edge-triggered -- I mean the "naked" input to the core, not anything that
may be presented to the outside world by any local APIC present (IOW the
line at the *output* of the local APIC where one is present).
There's more confusion about the ExtINTA mode (even the name itself is
spelled differently as ExtINTA vs ExtINT across various documents) as its
trigger mode is implied and not configurable with the vector/redirection
table entry's trigger-mode bit and various APIC implementations treat it
differently and hardwire as either edge-triggered or level-triggered as
the designers saw fit.
> > No, this is about the PIC, not the CPU interrupt inputs.
>
> I see, the interrupt is still sent to the processor; but IRR reflects
> that status of the input line, not a "pending interrupt" status.
Not really, this is still a "pending interrupt" status.
For level-triggered inputs the state of IRR bits do indeed follow the
respective IRx inputs (taking the IMR into account). For edge-triggered
inputs the relevant IRR bit is set by a leading edge on its corresponding
IRx input and cleared when the interrupt is acknowledged (either with an
INTA bus cycle or by a data read bus cycle issued to the PIC armed with an
OCW3 that has had the POLL command bit set) OR with a trailing edge on IRx
(again, all this takes the IMR into account). At this point another
leading edge is required for the IRR bit to be set again, that is merely
keeping the IRx input's level active won't trigger another interrupt.
Maciej
- [Qemu-devel] [PATCH v5 1/6] fix some debug printf format strings, (continued)
- [Qemu-devel] [PATCH v5 1/6] fix some debug printf format strings, Matthew Ogilvie, 2012/09/09
- [Qemu-devel] [PATCH v5 3/6] qemu-options.hx: mention retrace= VGA option, Matthew Ogilvie, 2012/09/09
- [Qemu-devel] [PATCH v5 2/6] vl: fix -hdachs/-hda argument order parsing issues, Matthew Ogilvie, 2012/09/09
- [Qemu-devel] [PATCH v5 4/6] vga: add some optional CGA compatibility hacks, Matthew Ogilvie, 2012/09/09
- [Qemu-devel] [PATCH v5 6/6] i8259: refactor pic_set_irq level logic, Matthew Ogilvie, 2012/09/09
- [Qemu-devel] [PATCH v5 5/6] i8259: fix so that dropping IRQ level always clears the interrupt request, Matthew Ogilvie, 2012/09/09
- Re: [Qemu-devel] [PATCH v5 5/6] i8259: fix so that dropping IRQ level always clears the interrupt request, Matthew Ogilvie, 2012/09/11
- Re: [Qemu-devel] [PATCH v5 5/6] i8259: fix so that dropping IRQ level always clears the interrupt request, Jan Kiszka, 2012/09/11
- Re: [Qemu-devel] [PATCH v5 5/6] i8259: fix so that dropping IRQ level always clears the interrupt request, Avi Kivity, 2012/09/11