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[Qemu-devel] [PATCH 021/126] target-s390: Convert LOAD LOGICAL IMMEDIATE
From: |
Richard Henderson |
Subject: |
[Qemu-devel] [PATCH 021/126] target-s390: Convert LOAD LOGICAL IMMEDIATE |
Date: |
Sun, 9 Sep 2012 14:04:39 -0700 |
Signed-off-by: Richard Henderson <address@hidden>
---
target-s390x/insn-data.def | 7 +++++++
target-s390x/translate.c | 42 ++++++++++++------------------------------
2 files changed, 19 insertions(+), 30 deletions(-)
diff --git a/target-s390x/insn-data.def b/target-s390x/insn-data.def
index 06d0ad8..9433d3d 100644
--- a/target-s390x/insn-data.def
+++ b/target-s390x/insn-data.def
@@ -168,6 +168,13 @@
/* LOAD LOGICAL HALFWORD RELATIVE LONG */
C(0xc402, LLHRL, RIL_b, GIE, 0, ri2, new, r1_32, ld16u, 0)
C(0xc406, LLGHRL, RIL_b, GIE, 0, ri2, r1, 0, ld16u, 0)
+/* LOAD LOGICAL IMMEDATE */
+ D(0xc00e, LLIHF, RIL_a, EI, 0, i2_32u_shl, 0, r1, mov2, 0, 32)
+ D(0xc00f, LLILF, RIL_a, EI, 0, i2_32u_shl, 0, r1, mov2, 0, 0)
+ D(0xa50c, LLIHH, RI_a, Z, 0, i2_16u_shl, 0, r1, mov2, 0, 48)
+ D(0xa50d, LLIHL, RI_a, Z, 0, i2_16u_shl, 0, r1, mov2, 0, 32)
+ D(0xa50e, LLILH, RI_a, Z, 0, i2_16u_shl, 0, r1, mov2, 0, 16)
+ D(0xa50f, LLILL, RI_a, Z, 0, i2_16u_shl, 0, r1, mov2, 0, 0)
/* MULTIPLY */
C(0x1c00, MR, RR_a, Z, r1p1_32s, r2_32s, new, r1_D32, mul, 0)
diff --git a/target-s390x/translate.c b/target-s390x/translate.c
index 1c83009..8233bed 100644
--- a/target-s390x/translate.c
+++ b/target-s390x/translate.c
@@ -2026,26 +2026,6 @@ static void disas_a5(DisasContext *s, int op, int r1,
int i2)
tcg_temp_free_i32(tmp32);
tcg_temp_free_i64(tmp);
break;
- case 0xc: /* LLIHH R1,I2 [RI] */
- tmp = tcg_const_i64( ((uint64_t)i2) << 48 );
- store_reg(r1, tmp);
- tcg_temp_free_i64(tmp);
- break;
- case 0xd: /* LLIHL R1,I2 [RI] */
- tmp = tcg_const_i64( ((uint64_t)i2) << 32 );
- store_reg(r1, tmp);
- tcg_temp_free_i64(tmp);
- break;
- case 0xe: /* LLILH R1,I2 [RI] */
- tmp = tcg_const_i64( ((uint64_t)i2) << 16 );
- store_reg(r1, tmp);
- tcg_temp_free_i64(tmp);
- break;
- case 0xf: /* LLILL R1,I2 [RI] */
- tmp = tcg_const_i64(i2);
- store_reg(r1, tmp);
- tcg_temp_free_i64(tmp);
- break;
default:
LOG_DISAS("illegal a5 operation 0x%x\n", op);
gen_illegal_opcode(s);
@@ -3027,16 +3007,6 @@ static void disas_c0(DisasContext *s, int op, int r1,
int i2)
tcg_temp_free_i64(tmp);
tcg_temp_free_i32(tmp32_1);
break;
- case 0xe: /* LLIHF R1,I2 [RIL] */
- tmp = tcg_const_i64(((uint64_t)(uint32_t)i2) << 32);
- store_reg(r1, tmp);
- tcg_temp_free_i64(tmp);
- break;
- case 0xf: /* LLILF R1,I2 [RIL] */
- tmp = tcg_const_i64((uint32_t)i2);
- store_reg(r1, tmp);
- tcg_temp_free_i64(tmp);
- break;
default:
LOG_DISAS("illegal c0 operation 0x%x\n", op);
gen_illegal_opcode(s);
@@ -4682,6 +4652,18 @@ static void in2_i2_32u(DisasContext *s, DisasFields *f,
DisasOps *o)
o->in2 = tcg_const_i64((uint32_t)get_field(f, i2));
}
+static void in2_i2_16u_shl(DisasContext *s, DisasFields *f, DisasOps *o)
+{
+ uint64_t i2 = (uint16_t)get_field(f, i2);
+ o->in2 = tcg_const_i64(i2 << s->insn->data);
+}
+
+static void in2_i2_32u_shl(DisasContext *s, DisasFields *f, DisasOps *o)
+{
+ uint64_t i2 = (uint32_t)get_field(f, i2);
+ o->in2 = tcg_const_i64(i2 << s->insn->data);
+}
+
/* ====================================================================== */
/* Find opc within the table of insns. This is formulated as a switch
--
1.7.11.4
- [Qemu-devel] [PATCH 014/126] target-s390: Convert MULTIPLY, (continued)
- [Qemu-devel] [PATCH 014/126] target-s390: Convert MULTIPLY, Richard Henderson, 2012/09/09
- [Qemu-devel] [PATCH 010/126] target-s390: Reorg exception handling, Richard Henderson, 2012/09/09
- [Qemu-devel] [PATCH 020/126] target-s390: Convert LOAD AND TEST, Richard Henderson, 2012/09/09
- [Qemu-devel] [PATCH 016/126] target-s390: Convert COMPARE, COMPARE LOGICAL, Richard Henderson, 2012/09/09
- [Qemu-devel] [PATCH 008/126] target-s390: Add format based disassassmbly infrastructure, Richard Henderson, 2012/09/09
- [Qemu-devel] [PATCH 022/126] target-s390: Convert LOAD COMPLIMENT, POSITIVE, NEGATIVE, Richard Henderson, 2012/09/09
- [Qemu-devel] [PATCH 023/126] target-s390: Convert AND, OR, XOR, INSERT IMMEDIATE, Richard Henderson, 2012/09/09
- [Qemu-devel] [PATCH 019/126] target-s390: Convert LOAD (LOGICAL) BYTE, CHARACTER, HALFWORD, Richard Henderson, 2012/09/09
- [Qemu-devel] [PATCH 024/126] target-s390: Convert STORE, Richard Henderson, 2012/09/09
- [Qemu-devel] [PATCH 026/126] target-s390: Convert BRANCH AND SAVE, Richard Henderson, 2012/09/09
- [Qemu-devel] [PATCH 021/126] target-s390: Convert LOAD LOGICAL IMMEDIATE,
Richard Henderson <=
- [Qemu-devel] [PATCH 025/126] target-s390: Convert ADD LOGICAL CARRY and SUBTRACT LOGICAL BORROW, Richard Henderson, 2012/09/09
- [Qemu-devel] [PATCH 027/126] target-s390: Convert BRANCH ON CONDITION, Richard Henderson, 2012/09/09
- [Qemu-devel] [PATCH 032/126] target-s390: Convert SET ADDRESSING MODE, Richard Henderson, 2012/09/09
- [Qemu-devel] [PATCH 030/126] target-s390: Send signals for divide, Richard Henderson, 2012/09/09
- [Qemu-devel] [PATCH 029/126] target-s390: Convert DIVIDE, Richard Henderson, 2012/09/09
- [Qemu-devel] [PATCH 028/126] target-s390: Convert BRANCH ON COUNT, Richard Henderson, 2012/09/09
- [Qemu-devel] [PATCH 031/126] target-s390: Convert TEST UNDER MASK, Richard Henderson, 2012/09/09
- [Qemu-devel] [PATCH 034/126] target-s390: Convert MOVE LONG, Richard Henderson, 2012/09/09
- [Qemu-devel] [PATCH 036/126] target-s390: Convert INSERT CHARACTER, Richard Henderson, 2012/09/09
- [Qemu-devel] [PATCH 035/126] target-s390: Convert FP LOAD, Richard Henderson, 2012/09/09