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[Qemu-devel] [PATCH 12/15] target-arm: Use target_phys_addr_t in get_phy
From: |
Peter Maydell |
Subject: |
[Qemu-devel] [PATCH 12/15] target-arm: Use target_phys_addr_t in get_phys_addr() |
Date: |
Thu, 12 Jul 2012 14:36:53 +0100 |
In the implementation of get_phys_addr(), consistently use
target_phys_addr_t to hold the physical address rather than
uint32_t.
Signed-off-by: Peter Maydell <address@hidden>
---
target-arm/helper.c | 29 +++++++++++++++--------------
1 files changed, 15 insertions(+), 14 deletions(-)
diff --git a/target-arm/helper.c b/target-arm/helper.c
index 6bb6767..d66bc3e 100644
--- a/target-arm/helper.c
+++ b/target-arm/helper.c
@@ -7,7 +7,7 @@
#ifndef CONFIG_USER_ONLY
static inline int get_phys_addr(CPUARMState *env, uint32_t address,
int access_type, int is_user,
- uint32_t *phys_ptr, int *prot,
+ target_phys_addr_t *phys_ptr, int *prot,
target_ulong *page_size);
#endif
@@ -505,7 +505,7 @@ static int par_write(CPUARMState *env, const ARMCPRegInfo
*ri, uint64_t value)
/* get_phys_addr() isn't present for user-mode-only targets */
static int ats_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value)
{
- uint32_t phys_addr;
+ target_phys_addr_t phys_addr;
target_ulong page_size;
int prot;
int ret, is_user = ri->opc2 & 2;
@@ -1929,8 +1929,8 @@ static uint32_t get_level1_table_address(CPUARMState
*env, uint32_t address)
}
static int get_phys_addr_v5(CPUARMState *env, uint32_t address, int
access_type,
- int is_user, uint32_t *phys_ptr, int *prot,
- target_ulong *page_size)
+ int is_user, target_phys_addr_t *phys_ptr,
+ int *prot, target_ulong *page_size)
{
int code;
uint32_t table;
@@ -1939,7 +1939,7 @@ static int get_phys_addr_v5(CPUARMState *env, uint32_t
address, int access_type,
int ap;
int domain;
int domain_prot;
- uint32_t phys_addr;
+ target_phys_addr_t phys_addr;
/* Pagetable walk. */
/* Lookup l1 descriptor. */
@@ -2024,8 +2024,8 @@ do_fault:
}
static int get_phys_addr_v6(CPUARMState *env, uint32_t address, int
access_type,
- int is_user, uint32_t *phys_ptr, int *prot,
- target_ulong *page_size)
+ int is_user, target_phys_addr_t *phys_ptr,
+ int *prot, target_ulong *page_size)
{
int code;
uint32_t table;
@@ -2036,7 +2036,7 @@ static int get_phys_addr_v6(CPUARMState *env, uint32_t
address, int access_type,
int ap;
int domain = 0;
int domain_prot;
- uint32_t phys_addr;
+ target_phys_addr_t phys_addr;
/* Pagetable walk. */
/* Lookup l1 descriptor. */
@@ -2135,8 +2135,9 @@ do_fault:
return code | (domain << 4);
}
-static int get_phys_addr_mpu(CPUARMState *env, uint32_t address, int
access_type,
- int is_user, uint32_t *phys_ptr, int *prot)
+static int get_phys_addr_mpu(CPUARMState *env, uint32_t address,
+ int access_type, int is_user,
+ target_phys_addr_t *phys_ptr, int *prot)
{
int n;
uint32_t mask;
@@ -2197,7 +2198,7 @@ static int get_phys_addr_mpu(CPUARMState *env, uint32_t
address, int access_type
static inline int get_phys_addr(CPUARMState *env, uint32_t address,
int access_type, int is_user,
- uint32_t *phys_ptr, int *prot,
+ target_phys_addr_t *phys_ptr, int *prot,
target_ulong *page_size)
{
/* Fast Context Switch Extension. */
@@ -2226,7 +2227,7 @@ static inline int get_phys_addr(CPUARMState *env,
uint32_t address,
int cpu_arm_handle_mmu_fault (CPUARMState *env, target_ulong address,
int access_type, int mmu_idx)
{
- uint32_t phys_addr;
+ target_phys_addr_t phys_addr;
target_ulong page_size;
int prot;
int ret, is_user;
@@ -2236,7 +2237,7 @@ int cpu_arm_handle_mmu_fault (CPUARMState *env,
target_ulong address,
&page_size);
if (ret == 0) {
/* Map a single [sub]page. */
- phys_addr &= ~(uint32_t)0x3ff;
+ phys_addr &= ~(target_phys_addr_t)0x3ff;
address &= ~(uint32_t)0x3ff;
tlb_set_page (env, address, phys_addr, prot, mmu_idx, page_size);
return 0;
@@ -2258,7 +2259,7 @@ int cpu_arm_handle_mmu_fault (CPUARMState *env,
target_ulong address,
target_phys_addr_t cpu_get_phys_page_debug(CPUARMState *env, target_ulong addr)
{
- uint32_t phys_addr;
+ target_phys_addr_t phys_addr;
target_ulong page_size;
int prot;
int ret;
--
1.7.1
- [Qemu-devel] [PULL 00/15] target-arm queue, Peter Maydell, 2012/07/12
- [Qemu-devel] [PATCH 14/15] target-arm: Implement TTBCR changes for LPAE, Peter Maydell, 2012/07/12
- [Qemu-devel] [PATCH 04/15] target-arm: Fix TCG temp handling in 64 bit cp writes, Peter Maydell, 2012/07/12
- [Qemu-devel] [PATCH 07/15] target-arm: Implement privileged-execute-never (PXN), Peter Maydell, 2012/07/12
- [Qemu-devel] [PATCH 09/15] target-arm: Add AMAIR0, AMAIR1 LPAE cp15 registers, Peter Maydell, 2012/07/12
- [Qemu-devel] [PATCH 06/15] ARM: Make target_phys_addr_t 64 bits and physaddrs 40 bits, Peter Maydell, 2012/07/12
- [Qemu-devel] [PATCH 10/15] target-arm: Add 64 bit variants of DBGDRAR and DBGDSAR for LPAE, Peter Maydell, 2012/07/12
- [Qemu-devel] [PATCH 11/15] target-arm: Add 64 bit PAR, TTBR0, TTBR1 for LPAE, Peter Maydell, 2012/07/12
- [Qemu-devel] [PATCH 15/15] target-arm: Add support for long format translation table walks, Peter Maydell, 2012/07/12
- [Qemu-devel] [PATCH 03/15] target-arm: Fix some copy-and-paste errors in cp register names, Peter Maydell, 2012/07/12
- [Qemu-devel] [PATCH 12/15] target-arm: Use target_phys_addr_t in get_phys_addr(),
Peter Maydell <=
- [Qemu-devel] [PATCH 01/15] target-arm: Fix CP15 based WFI, Peter Maydell, 2012/07/12
- [Qemu-devel] [PATCH 08/15] target-arm: Extend feature flags to 64 bits, Peter Maydell, 2012/07/12
- [Qemu-devel] [PATCH 02/15] target-arm: Fix typo that meant TTBR1 accesses went to TTBR0, Peter Maydell, 2012/07/12
- [Qemu-devel] [PATCH 13/15] target-arm: Implement long-descriptor PAR format, Peter Maydell, 2012/07/12
- [Qemu-devel] [PATCH 05/15] hw/imx_avic.c: Avoid format error when target_phys_addr_t is 64 bits, Peter Maydell, 2012/07/12
- Re: [Qemu-devel] [PULL 00/15] target-arm queue, Blue Swirl, 2012/07/14