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[Qemu-devel] [PATCH 12/13] target-arm: Implement TTBCR changes for LPAE
From: |
Peter Maydell |
Subject: |
[Qemu-devel] [PATCH 12/13] target-arm: Implement TTBCR changes for LPAE |
Date: |
Thu, 28 Jun 2012 15:36:05 +0100 |
Implement the changes to the TTBCR register required for LPAE:
* many fewer bits should be RAZ/WI
* since TTBCR changes can result in a change of ASID, we must
flush the TLB on writes to it
Signed-off-by: Peter Maydell <address@hidden>
---
target-arm/helper.c | 15 ++++++++++++++-
1 files changed, 14 insertions(+), 1 deletions(-)
diff --git a/target-arm/helper.c b/target-arm/helper.c
index 55f9f8a..9ff0771 100644
--- a/target-arm/helper.c
+++ b/target-arm/helper.c
@@ -692,7 +692,20 @@ static const ARMCPRegInfo pmsav5_cp_reginfo[] = {
static int vmsa_ttbcr_write(CPUARMState *env, const ARMCPRegInfo *ri,
uint64_t value)
{
- value &= 7;
+ if (arm_feature(env, ARM_FEATURE_LPAE)) {
+ value &= ~((7 << 19) | (3 << 14) | (0xf << 3));
+ /* With LPAE the TTBCR could result in a change of ASID
+ * via the TTBCR.A1 bit, so do a TLB flush.
+ */
+ tlb_flush(env, 1);
+ } else {
+ value &= 7;
+ }
+ /* Note that we always calculate c2_mask and c2_base_mask, but
+ * they are only used for short-descriptor tables (ie if EAE is 0);
+ * for long-descriptor tables the TTBCR fields are used differently
+ * and the c2_mask and c2_base_mask values are meaningless.
+ */
env->cp15.c2_control = value;
env->cp15.c2_mask = ~(((uint32_t)0xffffffffu) >> value);
env->cp15.c2_base_mask = ~((uint32_t)0x3fffu >> value);
--
1.7.1
- [Qemu-devel] [PATCH 00/13] ARM: Add LPAE support, Peter Maydell, 2012/06/28
- [Qemu-devel] [PATCH 10/13] target-arm: Use target_phys_addr_t in get_phys_addr(), Peter Maydell, 2012/06/28
- [Qemu-devel] [PATCH 02/13] target-arm: Fix typo that meant TTBR1 accesses went to TTBR0, Peter Maydell, 2012/06/28
- [Qemu-devel] [PATCH 09/13] target-arm: Add 64 bit PAR, TTBR0, TTBR1 for LPAE, Peter Maydell, 2012/06/28
- [Qemu-devel] [PATCH 07/13] target-arm: Add AMAIR0, AMAIR1 LPAE cp15 registers, Peter Maydell, 2012/06/28
- [Qemu-devel] [PATCH 04/13] ARM: Make target_phys_addr_t 64 bits and physaddrs 40 bits, Peter Maydell, 2012/06/28
- [Qemu-devel] [PATCH 08/13] target-arm: Add 64 bit variants of DBGDRAR and DBGDSAR for LPAE, Peter Maydell, 2012/06/28
- [Qemu-devel] [PATCH 12/13] target-arm: Implement TTBCR changes for LPAE,
Peter Maydell <=
- [Qemu-devel] [PATCH 03/13] bitops.h: Add functions to extract and deposit bitfields, Peter Maydell, 2012/06/28
- [Qemu-devel] [PATCH 05/13] target-arm: Implement privileged-execute-never (PXN), Peter Maydell, 2012/06/28
- [Qemu-devel] [PATCH 11/13] target-arm: Implement long-descriptor PAR format, Peter Maydell, 2012/06/28
- [Qemu-devel] [PATCH 01/13] hw/cadence_gem: Make rx_desc_addr and tx_desc_addr uint32_t, Peter Maydell, 2012/06/28
- [Qemu-devel] [PATCH 13/13] target-arm: Add support for long format translation table walks, Peter Maydell, 2012/06/28
- [Qemu-devel] [PATCH 06/13] target-arm: Extend feature flags to 64 bits, Peter Maydell, 2012/06/28