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[Qemu-devel] [PATCH 26/33] target-arm: Convert cp15 crn=0 crm={1, 2} fea
From: |
Peter Maydell |
Subject: |
[Qemu-devel] [PATCH 26/33] target-arm: Convert cp15 crn=0 crm={1, 2} feature registers |
Date: |
Wed, 20 Jun 2012 13:27:14 +0100 |
Convert the cp15 crn=0 crm={1,2} features registers to
the new cp reg framework.
Signed-off-by: Peter Maydell <address@hidden>
---
target-arm/cpu.c | 14 -----------
target-arm/cpu.h | 2 -
target-arm/helper.c | 62 ++++++++++++++++++++++++++++++++++++++++++++------
3 files changed, 54 insertions(+), 24 deletions(-)
diff --git a/target-arm/cpu.c b/target-arm/cpu.c
index d84db53..f9b3046 100644
--- a/target-arm/cpu.c
+++ b/target-arm/cpu.c
@@ -77,20 +77,6 @@ static void arm_cpu_reset(CPUState *s)
env->vfp.xregs[ARM_VFP_MVFR0] = cpu->mvfr0;
env->vfp.xregs[ARM_VFP_MVFR1] = cpu->mvfr1;
env->cp15.c0_cachetype = cpu->ctr;
- env->cp15.c0_c1[0] = cpu->id_pfr0;
- env->cp15.c0_c1[1] = cpu->id_pfr1;
- env->cp15.c0_c1[2] = cpu->id_dfr0;
- env->cp15.c0_c1[3] = cpu->id_afr0;
- env->cp15.c0_c1[4] = cpu->id_mmfr0;
- env->cp15.c0_c1[5] = cpu->id_mmfr1;
- env->cp15.c0_c1[6] = cpu->id_mmfr2;
- env->cp15.c0_c1[7] = cpu->id_mmfr3;
- env->cp15.c0_c2[0] = cpu->id_isar0;
- env->cp15.c0_c2[1] = cpu->id_isar1;
- env->cp15.c0_c2[2] = cpu->id_isar2;
- env->cp15.c0_c2[3] = cpu->id_isar3;
- env->cp15.c0_c2[4] = cpu->id_isar4;
- env->cp15.c0_c2[5] = cpu->id_isar5;
env->cp15.c0_clid = cpu->clidr;
memcpy(env->cp15.c0_ccsid, cpu->ccsidr, ARRAY_SIZE(cpu->ccsidr));
diff --git a/target-arm/cpu.h b/target-arm/cpu.h
index 02d86ca..0953543 100644
--- a/target-arm/cpu.h
+++ b/target-arm/cpu.h
@@ -111,8 +111,6 @@ typedef struct CPUARMState {
uint32_t c0_ccsid[16]; /* Cache size. */
uint32_t c0_clid; /* Cache level. */
uint32_t c0_cssel; /* Cache size selection. */
- uint32_t c0_c1[8]; /* Feature registers. */
- uint32_t c0_c2[8]; /* Instruction set registers. */
uint32_t c1_sys; /* System control register. */
uint32_t c1_coproc; /* Coprocessor access register. */
uint32_t c1_xscaleauxcr; /* XScale auxiliary control register. */
diff --git a/target-arm/helper.c b/target-arm/helper.c
index 00934cd..11b2ad9 100644
--- a/target-arm/helper.c
+++ b/target-arm/helper.c
@@ -825,6 +825,60 @@ void register_cp_regs_for_features(ARMCPU *cpu)
define_arm_cp_regs(cpu, cp_reginfo);
if (arm_feature(env, ARM_FEATURE_V6)) {
+ /* The ID registers all have impdef reset values */
+ ARMCPRegInfo v6_idregs[] = {
+ { .name = "ID_PFR0", .cp = 15, .crn = 0, .crm = 1,
+ .opc1 = 0, .opc2 = 0, .access = PL1_R, .type = ARM_CP_CONST,
+ .resetvalue = cpu->id_pfr0 },
+ { .name = "ID_PFR1", .cp = 15, .crn = 0, .crm = 1,
+ .opc1 = 0, .opc2 = 1, .access = PL1_R, .type = ARM_CP_CONST,
+ .resetvalue = cpu->id_pfr1 },
+ { .name = "ID_DFR0", .cp = 15, .crn = 0, .crm = 1,
+ .opc1 = 0, .opc2 = 2, .access = PL1_R, .type = ARM_CP_CONST,
+ .resetvalue = cpu->id_dfr0 },
+ { .name = "ID_AFR0", .cp = 15, .crn = 0, .crm = 1,
+ .opc1 = 0, .opc2 = 3, .access = PL1_R, .type = ARM_CP_CONST,
+ .resetvalue = cpu->id_afr0 },
+ { .name = "ID_MMFR0", .cp = 15, .crn = 0, .crm = 1,
+ .opc1 = 0, .opc2 = 4, .access = PL1_R, .type = ARM_CP_CONST,
+ .resetvalue = cpu->id_mmfr0 },
+ { .name = "ID_MMFR1", .cp = 15, .crn = 0, .crm = 1,
+ .opc1 = 0, .opc2 = 5, .access = PL1_R, .type = ARM_CP_CONST,
+ .resetvalue = cpu->id_mmfr1 },
+ { .name = "ID_MMFR2", .cp = 15, .crn = 0, .crm = 1,
+ .opc1 = 0, .opc2 = 6, .access = PL1_R, .type = ARM_CP_CONST,
+ .resetvalue = cpu->id_mmfr2 },
+ { .name = "ID_MMFR3", .cp = 15, .crn = 0, .crm = 1,
+ .opc1 = 0, .opc2 = 7, .access = PL1_R, .type = ARM_CP_CONST,
+ .resetvalue = cpu->id_mmfr3 },
+ { .name = "ID_ISAR0", .cp = 15, .crn = 0, .crm = 2,
+ .opc1 = 0, .opc2 = 0, .access = PL1_R, .type = ARM_CP_CONST,
+ .resetvalue = cpu->id_isar0 },
+ { .name = "ID_ISAR1", .cp = 15, .crn = 0, .crm = 2,
+ .opc1 = 0, .opc2 = 1, .access = PL1_R, .type = ARM_CP_CONST,
+ .resetvalue = cpu->id_isar1 },
+ { .name = "ID_ISAR2", .cp = 15, .crn = 0, .crm = 2,
+ .opc1 = 0, .opc2 = 2, .access = PL1_R, .type = ARM_CP_CONST,
+ .resetvalue = cpu->id_isar2 },
+ { .name = "ID_ISAR3", .cp = 15, .crn = 0, .crm = 2,
+ .opc1 = 0, .opc2 = 3, .access = PL1_R, .type = ARM_CP_CONST,
+ .resetvalue = cpu->id_isar3 },
+ { .name = "ID_ISAR4", .cp = 15, .crn = 0, .crm = 2,
+ .opc1 = 0, .opc2 = 4, .access = PL1_R, .type = ARM_CP_CONST,
+ .resetvalue = cpu->id_isar4 },
+ { .name = "ID_ISAR5", .cp = 15, .crn = 0, .crm = 2,
+ .opc1 = 0, .opc2 = 5, .access = PL1_R, .type = ARM_CP_CONST,
+ .resetvalue = cpu->id_isar5 },
+ /* 6..7 are as yet unallocated and must RAZ */
+ { .name = "ID_ISAR6", .cp = 15, .crn = 0, .crm = 2,
+ .opc1 = 0, .opc2 = 6, .access = PL1_R, .type = ARM_CP_CONST,
+ .resetvalue = 0 },
+ { .name = "ID_ISAR7", .cp = 15, .crn = 0, .crm = 2,
+ .opc1 = 0, .opc2 = 7, .access = PL1_R, .type = ARM_CP_CONST,
+ .resetvalue = 0 },
+ REGINFO_SENTINEL
+ };
+ define_arm_cp_regs(cpu, v6_idregs);
define_arm_cp_regs(cpu, v6_cp_reginfo);
} else {
define_arm_cp_regs(cpu, not_v6_cp_reginfo);
@@ -2064,14 +2118,6 @@ uint32_t HELPER(get_cp15)(CPUARMState *env, uint32_t
insn)
default:
goto bad_reg;
}
- case 1:
- if (!arm_feature(env, ARM_FEATURE_V6))
- goto bad_reg;
- return env->cp15.c0_c1[op2];
- case 2:
- if (!arm_feature(env, ARM_FEATURE_V6))
- goto bad_reg;
- return env->cp15.c0_c2[op2];
case 3: case 4: case 5: case 6: case 7:
return 0;
default:
--
1.7.1
- [Qemu-devel] [PATCH 13/33] target-arm: Convert generic timer cp15 regs, (continued)
- [Qemu-devel] [PATCH 13/33] target-arm: Convert generic timer cp15 regs, Peter Maydell, 2012/06/20
- [Qemu-devel] [PATCH 10/33] target-arm: Convert WFI/barriers special cases to cp_reginfo, Peter Maydell, 2012/06/20
- [Qemu-devel] [PATCH 14/33] target-arm: Convert cp15 c3 register, Peter Maydell, 2012/06/20
- [Qemu-devel] [PATCH 32/33] target-arm: Remove remaining old cp15 infrastructure, Peter Maydell, 2012/06/20
- [Qemu-devel] [PATCH 09/33] target-arm: Convert TEECR, TEEHBR to new scheme, Peter Maydell, 2012/06/20
- [Qemu-devel] [PATCH 03/33] hw/pxa2xx: Convert cp14 perf registers to new scheme, Peter Maydell, 2012/06/20
- [Qemu-devel] [PATCH 31/33] target-arm: Move block cache ops to new cp15 framework, Peter Maydell, 2012/06/20
- [Qemu-devel] [PATCH 22/33] target-arm: convert cp15 crn=7 registers, Peter Maydell, 2012/06/20
- [Qemu-devel] [PATCH 08/33] target-arm: Convert debug registers to cp_reginfo, Peter Maydell, 2012/06/20
- [Qemu-devel] [PATCH 30/33] target-arm: Remove c0_cachetype CPUARMState field, Peter Maydell, 2012/06/20
- [Qemu-devel] [PATCH 26/33] target-arm: Convert cp15 crn=0 crm={1, 2} feature registers,
Peter Maydell <=
- [Qemu-devel] [PATCH 02/33] target-arm: initial coprocessor register framework, Peter Maydell, 2012/06/20
- [Qemu-devel] [PATCH 28/33] target-arm: Convert MPIDR, Peter Maydell, 2012/06/20
- [Qemu-devel] [PATCH 16/33] target-arm: Convert cp15 crn=2 registers, Peter Maydell, 2012/06/20
- [Qemu-devel] [PATCH 19/33] target-arm: Convert cp15 crn=15 registers, Peter Maydell, 2012/06/20
- [Qemu-devel] [PATCH 04/33] hw/pxa2xx.c: Convert CLKCFG and PWRMODE cp14 regs, Peter Maydell, 2012/06/20
- [Qemu-devel] [PATCH 20/33] target-arm: Convert cp15 MMU TLB control, Peter Maydell, 2012/06/20
- [Qemu-devel] [PATCH 25/33] target-arm: Convert cp15 crn=1 registers, Peter Maydell, 2012/06/20
- [Qemu-devel] [PATCH 06/33] target-arm: Remove old cpu_arm_set_cp_io infrastructure, Peter Maydell, 2012/06/20
- [Qemu-devel] [PATCH 29/33] target-arm: Convert final ID registers, Peter Maydell, 2012/06/20
- [Qemu-devel] [PATCH 15/33] target-arm: Convert MMU fault status cp15 registers, Peter Maydell, 2012/06/20