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[Qemu-devel] [PATCH v2 14/17] Openrisc: add gdb stub support
From: |
Jia Liu |
Subject: |
[Qemu-devel] [PATCH v2 14/17] Openrisc: add gdb stub support |
Date: |
Sun, 27 May 2012 13:32:56 +0800 |
add gdb stub support for openrisc.
Signed-off-by: Jia Liu <address@hidden>
---
gdbstub.c | 64 +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
1 file changed, 64 insertions(+)
diff --git a/gdbstub.c b/gdbstub.c
index 6a77a66..98a0d18 100644
--- a/gdbstub.c
+++ b/gdbstub.c
@@ -1155,6 +1155,68 @@ static int cpu_gdb_write_register(CPUMIPSState *env,
uint8_t *mem_buf, int n)
return sizeof(target_ulong);
}
+#elif defined(TARGET_OPENRISC)
+
+#define NUM_CORE_REGS (32 + 3)
+
+static int cpu_gdb_read_register(CPUOpenriscState *env, uint8_t *mem_buf, int
n)
+{
+ if (n < 32) {
+ GET_REG32(env->gpr[n]);
+ } else {
+ switch (n) {
+ case 32: /* PPC */
+ GET_REG32(env->ppc);
+ break;
+
+ case 33: /* NPC */
+ GET_REG32(env->npc);
+ break;
+
+ case 34: /* SR */
+ GET_REG32(env->sr);
+ break;
+
+ default:
+ break;
+ }
+ }
+ return 0;
+}
+
+static int cpu_gdb_write_register(CPUOpenriscState *env,
+ uint8_t *mem_buf, int n)
+{
+ uint32_t tmp;
+
+ if (n > NUM_CORE_REGS) {
+ return 0;
+ }
+
+ tmp = ldl_p(mem_buf);
+
+ if (n < 32) {
+ env->gpr[n] = tmp;
+ } else {
+ switch (n) {
+ case 32: /* PPC */
+ env->ppc = tmp;
+ break;
+
+ case 33: /* NPC */
+ env->npc = tmp;
+ break;
+
+ case 34: /* SR */
+ env->sr = tmp;
+ break;
+
+ default:
+ break;
+ }
+ }
+ return 4;
+}
#elif defined (TARGET_SH4)
/* Hint: Use "set architecture sh4" in GDB to see fpu registers */
@@ -1924,6 +1986,8 @@ static void gdb_set_cpu_pc(GDBState *s, target_ulong pc)
}
#elif defined (TARGET_MICROBLAZE)
s->c_cpu->sregs[SR_PC] = pc;
+#elif defined(TARGET_OPENRISC)
+ s->c_cpu->pc = pc;
#elif defined (TARGET_CRIS)
s->c_cpu->pc = pc;
#elif defined (TARGET_ALPHA)
--
1.7.9.5
- [Qemu-devel] [PATCH v2 04/17] Openrisc: add MMU support, (continued)
- [Qemu-devel] [PATCH v2 04/17] Openrisc: add MMU support, Jia Liu, 2012/05/27
- [Qemu-devel] [PATCH v2 06/17] Openrisc: add exception support, Jia Liu, 2012/05/27
- [Qemu-devel] [PATCH v2 07/17] Openrisc: add int instruction helpers, Jia Liu, 2012/05/27
- [Qemu-devel] [PATCH v2 08/17] Openrisc: add float instruction helpers, Jia Liu, 2012/05/27
- [Qemu-devel] [PATCH v2 09/17] Openrisc: add instruction translation routines, Jia Liu, 2012/05/27
- [Qemu-devel] [PATCH v2 10/17] Openrisc: add Programmable Interrupt Controller, Jia Liu, 2012/05/27
- [Qemu-devel] [PATCH v2 11/17] Openrisc: add a timer, Jia Liu, 2012/05/27
- [Qemu-devel] [PATCH v2 12/17] Openrisc: add a simulator board, Jia Liu, 2012/05/27
- [Qemu-devel] [PATCH v2 13/17] Openrisc: add system instruction helpers, Jia Liu, 2012/05/27
- [Qemu-devel] [PATCH v2 14/17] Openrisc: add gdb stub support,
Jia Liu <=
- [Qemu-devel] [PATCH v2 16/17] Openrisc: add linux user support, Jia Liu, 2012/05/27
- [Qemu-devel] [PATCH v2 17/17] Openrisc: add testcases, Jia Liu, 2012/05/27
- [Qemu-devel] [PATCH v2 15/17] Openrisc: add linux syscall, signal and termbits, Jia Liu, 2012/05/27
- Re: [Qemu-devel] [PATCH v2 00/17] Qemu Openrisc support, Stefan Weil, 2012/05/27
- [Qemu-devel] [PATCH v2 05/17] Openrisc: add interrupt support, Jia Liu, 2012/05/27