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[Qemu-devel] [PATCH 5/9] hw/arm_gic: Add qdev property for GIC revision
From: |
Peter Maydell |
Subject: |
[Qemu-devel] [PATCH 5/9] hw/arm_gic: Add qdev property for GIC revision |
Date: |
Wed, 2 May 2012 18:12:08 +0100 |
GIC behaviour can be different between revision 1 and
2 of the architectural GIC specification; we also have
to handle the legacy 11MPCore GIC, which is different
again in some places. Introduce a qdev property so we
can behave appropriately.
Signed-off-by: Peter Maydell <address@hidden>
---
hw/a15mpcore.c | 1 +
hw/arm11mpcore.c | 2 ++
hw/arm_gic.c | 10 ++++++++++
hw/armv7m_nvic.c | 2 ++
4 files changed, 15 insertions(+), 0 deletions(-)
diff --git a/hw/a15mpcore.c b/hw/a15mpcore.c
index 5a7b365..fc0a02a 100644
--- a/hw/a15mpcore.c
+++ b/hw/a15mpcore.c
@@ -44,6 +44,7 @@ static int a15mp_priv_init(SysBusDevice *dev)
s->gic = qdev_create(NULL, "arm_gic");
qdev_prop_set_uint32(s->gic, "num-cpu", s->num_cpu);
qdev_prop_set_uint32(s->gic, "num-irq", s->num_irq);
+ qdev_prop_set_uint32(s->gic, "revision", 2);
qdev_init_nofail(s->gic);
busdev = sysbus_from_qdev(s->gic);
diff --git a/hw/arm11mpcore.c b/hw/arm11mpcore.c
index c528d7a..1bff3d3 100644
--- a/hw/arm11mpcore.c
+++ b/hw/arm11mpcore.c
@@ -123,6 +123,8 @@ static int mpcore_priv_init(SysBusDevice *dev)
s->gic = qdev_create(NULL, "arm_gic");
qdev_prop_set_uint32(s->gic, "num-cpu", s->num_cpu);
qdev_prop_set_uint32(s->gic, "num-irq", s->num_irq);
+ /* Request the legacy 11MPCore GIC behaviour: */
+ qdev_prop_set_uint32(s->gic, "revision", 0);
qdev_init_nofail(s->gic);
/* Pass through outbound IRQ lines from the GIC */
diff --git a/hw/arm_gic.c b/hw/arm_gic.c
index 2ec10ce..ad72ac6 100644
--- a/hw/arm_gic.c
+++ b/hw/arm_gic.c
@@ -119,8 +119,13 @@ typedef struct gic_state
struct gic_state *backref[NCPU];
MemoryRegion cpuiomem[NCPU+1]; /* CPU interfaces */
uint32_t num_irq;
+ uint32_t revision;
} gic_state;
+/* The special cases for the revision property: */
+#define REV_11MPCORE 0
+#define REV_NVIC 0xffffffff
+
static inline int gic_get_current_cpu(gic_state *s)
{
if (s->num_cpu > 1) {
@@ -880,6 +885,11 @@ static int arm_gic_init(SysBusDevice *dev)
static Property arm_gic_properties[] = {
DEFINE_PROP_UINT32("num-cpu", gic_state, num_cpu, 1),
DEFINE_PROP_UINT32("num-irq", gic_state, num_irq, 32),
+ /* Revision can be 1 or 2 for GIC architecture specification
+ * versions 1 or 2, or 0 to indicate the legacy 11MPCore GIC.
+ * (Internally, 0xffffffff also indicates "not a GIC but an NVIC".)
+ */
+ DEFINE_PROP_UINT32("revision", gic_state, revision, 1),
DEFINE_PROP_END_OF_LIST(),
};
diff --git a/hw/armv7m_nvic.c b/hw/armv7m_nvic.c
index 747e245..4c130f1 100644
--- a/hw/armv7m_nvic.c
+++ b/hw/armv7m_nvic.c
@@ -447,6 +447,8 @@ static int armv7m_nvic_init(SysBusDevice *dev)
/* The NVIC always has only one CPU */
s->gic.num_cpu = 1;
+ /* Tell the common code we're an NVIC */
+ s->gic.revision = 0xffffffff;
gic_init(&s->gic, s->num_irq);
/* The NVIC and system controller register area looks like this:
* 0..0xff : system control registers, including systick
--
1.7.1
- Re: [Qemu-devel] [PATCH 2/9] hw/arm_gic: Remove the special casing of NCPU for the NVIC, (continued)
- [Qemu-devel] [PATCH 1/9] hw/arm_gic: Remove NVIC ifdefs from gic_state struct, Peter Maydell, 2012/05/02
- [Qemu-devel] [PATCH 6/9] hw/arm_gic: Make CPU target registers RAZ/WI on uniprocessor, Peter Maydell, 2012/05/02
- [Qemu-devel] [PATCH 7/9] hw/arm_gic.c: Make NVIC interrupt numbering a runtime setting, Peter Maydell, 2012/05/02
- [Qemu-devel] [PATCH 3/9] hw/arm_gic: Move NVIC specific reset to armv7m_nvic_reset, Peter Maydell, 2012/05/02
- [Qemu-devel] [PATCH 8/9] hw/arm_gic: Move CPU interface memory region setup into arm_gic_init, Peter Maydell, 2012/05/02
- [Qemu-devel] [PATCH 9/9] hw/armv7m_nvic: Make the NVIC a freestanding class, Peter Maydell, 2012/05/02
- [Qemu-devel] [PATCH 4/9] hw/armv7m_nvic: Use MemoryRegions for NVIC specific registers, Peter Maydell, 2012/05/02
- [Qemu-devel] [PATCH 5/9] hw/arm_gic: Add qdev property for GIC revision,
Peter Maydell <=
- Re: [Qemu-devel] [PATCH 0/9] disentangle NVIC from ARM GIC, Peter Maydell, 2012/05/18