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[Qemu-devel] [PATCH 01/13] hw/arm_gic: Move NCPU definition to arm_gic.c
From: |
Peter Maydell |
Subject: |
[Qemu-devel] [PATCH 01/13] hw/arm_gic: Move NCPU definition to arm_gic.c |
Date: |
Wed, 4 Apr 2012 16:30:50 +0100 |
Move the NCPU definition to arm_gic.c: the maximum number
of CPU interfaces is defined by the GIC architecture specification
to be 8, so we don't need to have this #define in each of the
sources files which currently includes arm_gic.c.
Signed-off-by: Peter Maydell <address@hidden>
---
hw/a15mpcore.c | 8 +-------
hw/a9mpcore.c | 8 +-------
hw/arm11mpcore.c | 2 --
hw/arm_gic.c | 13 ++++++++++++-
hw/armv7m_nvic.c | 1 -
hw/exynos4210_gic.c | 9 ++++-----
hw/realview_gic.c | 4 +---
7 files changed, 19 insertions(+), 26 deletions(-)
diff --git a/hw/a15mpcore.c b/hw/a15mpcore.c
index 71142e5..67206ec 100644
--- a/hw/a15mpcore.c
+++ b/hw/a15mpcore.c
@@ -21,10 +21,8 @@
#include "sysbus.h"
/* Configuration for arm_gic.c:
- * max number of CPUs, how to ID current CPU
+ * how to ID current CPU
*/
-#define NCPU 4
-
static inline int gic_get_current_cpu(void)
{
return cpu_single_env->cpu_index;
@@ -45,10 +43,6 @@ static int a15mp_priv_init(SysBusDevice *dev)
{
A15MPPrivState *s = FROM_SYSBUSGIC(A15MPPrivState, dev);
- if (s->num_cpu > NCPU) {
- hw_error("a15mp_priv_init: num-cpu may not be more than %d\n", NCPU);
- }
-
gic_init(&s->gic, s->num_cpu, s->num_irq);
/* Memory map (addresses are offsets from PERIPHBASE):
diff --git a/hw/a9mpcore.c b/hw/a9mpcore.c
index 03b128c..5bbe3c7 100644
--- a/hw/a9mpcore.c
+++ b/hw/a9mpcore.c
@@ -11,10 +11,8 @@
#include "sysbus.h"
/* Configuration for arm_gic.c:
- * max number of CPUs, how to ID current CPU
+ * how to ID current CPU
*/
-#define NCPU 4
-
static inline int
gic_get_current_cpu(void)
{
@@ -149,10 +147,6 @@ static int a9mp_priv_init(SysBusDevice *dev)
SysBusDevice *busdev;
int i;
- if (s->num_cpu > NCPU) {
- hw_error("a9mp_priv_init: num-cpu may not be more than %d\n", NCPU);
- }
-
gic_init(&s->gic, s->num_cpu, s->num_irq);
s->mptimer = qdev_create(NULL, "arm_mptimer");
diff --git a/hw/arm11mpcore.c b/hw/arm11mpcore.c
index ba6a89d..99c1826 100644
--- a/hw/arm11mpcore.c
+++ b/hw/arm11mpcore.c
@@ -10,8 +10,6 @@
#include "sysbus.h"
#include "qemu-timer.h"
-#define NCPU 4
-
static inline int
gic_get_current_cpu(void)
{
diff --git a/hw/arm_gic.c b/hw/arm_gic.c
index 6b34c06..f64a001 100644
--- a/hw/arm_gic.c
+++ b/hw/arm_gic.c
@@ -15,6 +15,13 @@
#define GIC_MAXIRQ 1020
/* First 32 are private to each CPU (SGIs and PPIs). */
#define GIC_INTERNAL 32
+/* Maximum number of possible CPU interfaces, determined by GIC architecture */
+#ifdef NVIC
+#define NCPU 1
+#else
+#define NCPU 8
+#endif
+
//#define DEBUG_GIC
#ifdef DEBUG_GIC
@@ -50,7 +57,7 @@ typedef struct gic_irq_state
unsigned trigger:1; /* nonzero = edge triggered. */
} gic_irq_state;
-#define ALL_CPU_MASK ((1 << NCPU) - 1)
+#define ALL_CPU_MASK ((unsigned)(((1 << NCPU) - 1)))
#if NCPU > 1
#define NUM_CPU(s) ((s)->num_cpu)
#else
@@ -813,6 +820,10 @@ static void gic_init(gic_state *s, int num_irq)
#if NCPU > 1
s->num_cpu = num_cpu;
+ if (s->num_cpu > NCPU) {
+ hw_error("requested %u CPUs exceeds GIC maximum %d\n",
+ num_cpu, NCPU);
+ }
#endif
s->num_irq = num_irq + GIC_BASE_IRQ;
if (s->num_irq > GIC_MAXIRQ) {
diff --git a/hw/armv7m_nvic.c b/hw/armv7m_nvic.c
index 3210129..bdab709 100644
--- a/hw/armv7m_nvic.c
+++ b/hw/armv7m_nvic.c
@@ -15,7 +15,6 @@
#include "arm-misc.h"
#include "exec-memory.h"
-#define NCPU 1
#define NVIC 1
/* Only a single "CPU" interface is present. */
diff --git a/hw/exynos4210_gic.c b/hw/exynos4210_gic.c
index 3ba9063..426f540 100644
--- a/hw/exynos4210_gic.c
+++ b/hw/exynos4210_gic.c
@@ -174,7 +174,6 @@
combiner_grp_to_gic_id[64-EXYNOS4210_MAX_EXT_COMBINER_OUT_IRQ][8] = {
};
#define EXYNOS4210_GIC_NIRQ 160
-#define NCPU EXYNOS4210_NCPUS
#define EXYNOS4210_EXT_GIC_CPU_REGION_SIZE 0x10000
#define EXYNOS4210_EXT_GIC_DIST_REGION_SIZE 0x10000
@@ -275,8 +274,8 @@ typedef struct {
gic_state gic;
MemoryRegion cpu_container;
MemoryRegion dist_container;
- MemoryRegion cpu_alias[NCPU];
- MemoryRegion dist_alias[NCPU];
+ MemoryRegion cpu_alias[EXYNOS4210_NCPUS];
+ MemoryRegion dist_alias[EXYNOS4210_NCPUS];
uint32_t num_cpu;
} Exynos4210GicState;
@@ -359,7 +358,7 @@ type_init(exynos4210_gic_register_types)
typedef struct {
SysBusDevice busdev;
- qemu_irq pic_irq[NCPU]; /* output IRQs to PICs */
+ qemu_irq pic_irq[EXYNOS4210_NCPUS]; /* output IRQs to PICs */
uint32_t gpio_level[EXYNOS4210_IRQ_GATE_NINPUTS]; /* Input levels */
} Exynos4210IRQGateState;
@@ -424,7 +423,7 @@ static int exynos4210_irq_gate_init(SysBusDevice *dev)
EXYNOS4210_IRQ_GATE_NINPUTS);
/* Connect SysBusDev irqs to device specific irqs */
- for (i = 0; i < NCPU; i++) {
+ for (i = 0; i < EXYNOS4210_NCPUS; i++) {
sysbus_init_irq(dev, &s->pic_irq[i]);
}
diff --git a/hw/realview_gic.c b/hw/realview_gic.c
index 071ef13..d114242 100644
--- a/hw/realview_gic.c
+++ b/hw/realview_gic.c
@@ -9,8 +9,6 @@
#include "sysbus.h"
-#define NCPU 1
-
/* Only a single "CPU" interface is present. */
static inline int
gic_get_current_cpu(void)
@@ -40,7 +38,7 @@ static int realview_gic_init(SysBusDevice *dev)
* number of interrupt lines, so we don't need to expose this as
* a qdev property.
*/
- gic_init(&s->gic, 96);
+ gic_init(&s->gic, 1, 96);
realview_gic_map_setup(s);
sysbus_init_mmio(dev, &s->container);
return 0;
--
1.7.1
- [Qemu-devel] [PATCH 08/13] hw/exynos4210_gic.c: Convert to using sysbus GIC, (continued)
- [Qemu-devel] [PATCH 08/13] hw/exynos4210_gic.c: Convert to using sysbus GIC, Peter Maydell, 2012/04/04
- [Qemu-devel] [PATCH 05/13] hw/a15mpcore: switch to using sysbus GIC, Peter Maydell, 2012/04/04
- [Qemu-devel] [PATCH 13/13] hw/arm_gic.c: Remove stray hardcoded tab, Peter Maydell, 2012/04/04
- [Qemu-devel] [PATCH 11/13] hw/arm_gic.c: Use NVIC instead of LEGACY_INCLUDED_GIC define, Peter Maydell, 2012/04/04
- [Qemu-devel] [PATCH 04/13] arm_gic: Make the GIC its own sysbus device, Peter Maydell, 2012/04/04
- [Qemu-devel] [PATCH 03/13] hw/arm_gic.c: Expose PPI inputs as gpio inputs, Peter Maydell, 2012/04/04
- [Qemu-devel] [PATCH 09/13] hw/arm11mpcore: Convert to using sysbus GIC device, Peter Maydell, 2012/04/04
- [Qemu-devel] [PATCH 01/13] hw/arm_gic: Move NCPU definition to arm_gic.c,
Peter Maydell <=
- Re: [Qemu-devel] [PATCH 00/13] Convert ARM GIC to sysbus device, Evgeny Voevodin, 2012/04/05
- Re: [Qemu-devel] [PATCH 00/13] Convert ARM GIC to sysbus device, Peter Maydell, 2012/04/05