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[Qemu-devel] [PATCH v2 0/5] tcg-mips: Use TCG registers for the FPU
From: |
Richard Henderson |
Subject: |
[Qemu-devel] [PATCH v2 0/5] tcg-mips: Use TCG registers for the FPU |
Date: |
Fri, 30 Mar 2012 13:05:39 -0400 |
This is a re-base of a patch set sent in December. The only
real changes are CPUState -> CPUMIPSState. The commit message
for patch 4 describe the real intent.
This patch set is also available at
git://repo.or.cz/qemu/rth.git rth/mips/fpregs
r~
Richard Henderson (5):
target-mips: Set opn in gen_ldst_multiple.
target-mips: Fix MIPS_DEBUG.
target-mips: Pass DisasContext to fpr32 load/store routines
target-mips: Use TCG registers for the FPU.
target-mips: Add accessors for the two 32-bit halves of a 64-bit FPR
target-mips/translate.c | 547 +++++++++++++++++++++++++++--------------------
1 files changed, 318 insertions(+), 229 deletions(-)
--
1.7.7.6
- [Qemu-devel] [PATCH v2 0/5] tcg-mips: Use TCG registers for the FPU,
Richard Henderson <=
- [Qemu-devel] [PATCH 1/5] target-mips: Set opn in gen_ldst_multiple., Richard Henderson, 2012/03/30
- [Qemu-devel] [PATCH 2/5] target-mips: Fix MIPS_DEBUG., Richard Henderson, 2012/03/30
- [Qemu-devel] [PATCH 5/5] target-mips: Add accessors for the two 32-bit halves of a 64-bit FPR, Richard Henderson, 2012/03/30
- [Qemu-devel] [PATCH 4/5] target-mips: Use TCG registers for the FPU., Richard Henderson, 2012/03/30
- [Qemu-devel] [PATCH 3/5] target-mips: Pass DisasContext to fpr32 load/store routines, Richard Henderson, 2012/03/30