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[Qemu-devel] [PATCH 11/14] target-arm: Move cache ID register setup to c
From: |
Peter Maydell |
Subject: |
[Qemu-devel] [PATCH 11/14] target-arm: Move cache ID register setup to cpu specific init fns |
Date: |
Fri, 30 Mar 2012 13:51:47 +0100 |
Move cache ID register reset out of cpu_reset_model_id() by
creating a field for the reset value in ARMCPU and setting it
up in the cpu specific init functions.
Signed-off-by: Peter Maydell <address@hidden>
---
target-arm/cpu-qom.h | 2 ++
target-arm/cpu.c | 11 +++++++++++
target-arm/helper.c | 13 ++-----------
3 files changed, 15 insertions(+), 11 deletions(-)
diff --git a/target-arm/cpu-qom.h b/target-arm/cpu-qom.h
index efdc0a8..55dc920 100644
--- a/target-arm/cpu-qom.h
+++ b/target-arm/cpu-qom.h
@@ -82,6 +82,8 @@ typedef struct ARMCPU {
uint32_t id_isar3;
uint32_t id_isar4;
uint32_t id_isar5;
+ uint32_t clidr;
+ uint32_t ccsidr[16];
} ARMCPU;
static inline ARMCPU *arm_env_get_cpu(CPUARMState *env)
diff --git a/target-arm/cpu.c b/target-arm/cpu.c
index a58bda2..c2eb998 100644
--- a/target-arm/cpu.c
+++ b/target-arm/cpu.c
@@ -280,6 +280,10 @@ static void cortex_a8_initfn(Object *obj)
cpu->id_isar2 = 0x21232031;
cpu->id_isar3 = 0x11112131;
cpu->id_isar4 = 0x00111142;
+ cpu->clidr = (1 << 27) | (2 << 24) | 3;
+ cpu->ccsidr[0] = 0xe007e01a; /* 16k L1 dcache. */
+ cpu->ccsidr[1] = 0x2007e01a; /* 16k L1 icache. */
+ cpu->ccsidr[2] = 0xf0000000; /* No L2 icache. */
arm_cpu_postconfig_init(cpu);
}
@@ -314,6 +318,9 @@ static void cortex_a9_initfn(Object *obj)
cpu->id_isar2 = 0x21232041;
cpu->id_isar3 = 0x11112131;
cpu->id_isar4 = 0x00111142;
+ cpu->clidr = (1 << 27) | (2 << 24) | 3;
+ cpu->ccsidr[0] = 0xe00fe015; /* 16k L1 dcache. */
+ cpu->ccsidr[1] = 0x200fe015; /* 16k L1 icache. */
arm_cpu_postconfig_init(cpu);
}
@@ -346,6 +353,10 @@ static void cortex_a15_initfn(Object *obj)
cpu->id_isar2 = 0x21232041;
cpu->id_isar3 = 0x11112131;
cpu->id_isar4 = 0x10011142;
+ cpu->clidr = 0x0a200023;
+ cpu->ccsidr[0] = 0x701fe00a; /* 32K L1 dcache */
+ cpu->ccsidr[1] = 0x201fe00a; /* 32K L1 icache */
+ cpu->ccsidr[2] = 0x711fe07a; /* 4096K L2 unified cache */
arm_cpu_postconfig_init(cpu);
}
diff --git a/target-arm/helper.c b/target-arm/helper.c
index a94f09f..5c4cfee 100644
--- a/target-arm/helper.c
+++ b/target-arm/helper.c
@@ -26,21 +26,10 @@ static void cpu_reset_model_id(CPUARMState *env, uint32_t
id)
case ARM_CPUID_ARM11MPCORE:
break;
case ARM_CPUID_CORTEXA8:
- env->cp15.c0_clid = (1 << 27) | (2 << 24) | 3;
- env->cp15.c0_ccsid[0] = 0xe007e01a; /* 16k L1 dcache. */
- env->cp15.c0_ccsid[1] = 0x2007e01a; /* 16k L1 icache. */
- env->cp15.c0_ccsid[2] = 0xf0000000; /* No L2 icache. */
break;
case ARM_CPUID_CORTEXA9:
- env->cp15.c0_clid = (1 << 27) | (1 << 24) | 3;
- env->cp15.c0_ccsid[0] = 0xe00fe015; /* 16k L1 dcache. */
- env->cp15.c0_ccsid[1] = 0x200fe015; /* 16k L1 icache. */
break;
case ARM_CPUID_CORTEXA15:
- env->cp15.c0_clid = 0x0a200023;
- env->cp15.c0_ccsid[0] = 0x701fe00a; /* 32K L1 dcache */
- env->cp15.c0_ccsid[1] = 0x201fe00a; /* 32K L1 icache */
- env->cp15.c0_ccsid[2] = 0x711fe07a; /* 4096K L2 unified cache */
break;
case ARM_CPUID_CORTEXM3:
break;
@@ -114,6 +103,8 @@ void cpu_state_reset(CPUARMState *env)
env->cp15.c0_c2[4] = cpu->id_isar4;
env->cp15.c0_c2[5] = cpu->id_isar5;
env->cp15.c15_i_min = 0xff0;
+ env->cp15.c0_clid = cpu->clidr;
+ memcpy(env->cp15.c0_ccsid, cpu->ccsidr, ARRAY_SIZE(cpu->ccsidr));
if (arm_feature(env, ARM_FEATURE_IWMMXT)) {
env->iwmmxt.cregs[ARM_IWMMXT_wCID] = 0x69051000 | 'Q';
--
1.7.1
- [Qemu-devel] [PATCH 00/14] target-arm: Create QOM subclass per CPU implementation, Peter Maydell, 2012/03/30
- [Qemu-devel] [PATCH 07/14] target-arm: Drop JTAG_ID documentation, Peter Maydell, 2012/03/30
- [Qemu-devel] [PATCH 09/14] target-arm: Move feature register setup to per-CPU init fns, Peter Maydell, 2012/03/30
- [Qemu-devel] [PATCH 11/14] target-arm: Move cache ID register setup to cpu specific init fns,
Peter Maydell <=
- [Qemu-devel] [PATCH 13/14] target-arm: Move reset handling to arm_cpu_reset, Peter Maydell, 2012/03/30
- [Qemu-devel] [PATCH 01/14] target-arm: Add QOM subclasses for each ARM cpu implementation, Peter Maydell, 2012/03/30
- [Qemu-devel] [PATCH 08/14] target-arm: Move iWMMXT wCID reset to cpu_state_reset, Peter Maydell, 2012/03/30
- [Qemu-devel] [PATCH 10/14] target-arm: Move OMAP cp15_i_{max, min} reset to cpu_state_reset, Peter Maydell, 2012/03/30
- [Qemu-devel] [PATCH 12/14] target-arm: Drop cpu_reset_model_id(), Peter Maydell, 2012/03/30
- [Qemu-devel] [PATCH 14/14] target-arm: Move A9 config_base_address reset value to ARMCPU, Peter Maydell, 2012/03/30
- [Qemu-devel] [PATCH 04/14] target-arm: Move MVFR* setup to per cpu init fns, Peter Maydell, 2012/03/30
- [Qemu-devel] [PATCH 02/14] target-arm: Move feature bit settings to CPU init fns, Peter Maydell, 2012/03/30