[Top][All Lists]
[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]
[Qemu-devel] [PATCH V4 04/11] Add MIPS DSP Load instructions Support
From: |
Jia Liu |
Subject: |
[Qemu-devel] [PATCH V4 04/11] Add MIPS DSP Load instructions Support |
Date: |
Fri, 30 Mar 2012 11:17:05 +0800 |
Add MIPS DSP Load instructions Support.
Signed-off-by: Jia Liu <address@hidden>
---
target-mips/translate.c | 47 +++++++++++++++++++++++++++++++++++++++++++++++
1 files changed, 47 insertions(+), 0 deletions(-)
diff --git a/target-mips/translate.c b/target-mips/translate.c
index 8f8daf2..608f6de 100644
--- a/target-mips/translate.c
+++ b/target-mips/translate.c
@@ -312,6 +312,10 @@ enum {
OPC_MODU_G_2E = 0x23 | OPC_SPECIAL3,
OPC_DMOD_G_2E = 0x26 | OPC_SPECIAL3,
OPC_DMODU_G_2E = 0x27 | OPC_SPECIAL3,
+
+ /* MIPS DSP Load */
+ OPC_LX_DSP = 0x0A | OPC_SPECIAL3,
+
};
/* BSHFL opcodes */
@@ -336,6 +340,14 @@ enum {
OPC_BPOSGE32 = (0x1C << 16) | OPC_REGIMM,
};
+#define MASK_LX(op) (MASK_SPECIAL3(op) | (op & (0x1F << 6)))
+/* MIPS DSP Load */
+enum {
+ OPC_LBUX = (0x06 << 6) | OPC_LX_DSP,
+ OPC_LHX = (0x04 << 6) | OPC_LX_DSP,
+ OPC_LWX = (0x00 << 6) | OPC_LX_DSP,
+};
+
/* Coprocessor 0 (rs field) */
#define MASK_CP0(op) MASK_OP_MAJOR(op) | (op & (0x1F << 21))
@@ -12062,6 +12074,41 @@ static void decode_opc (CPUMIPSState *env,
DisasContext *ctx, int *is_branch)
check_insn(env, ctx, INSN_LOONGSON2E);
gen_loongson_integer(ctx, op1, rd, rs, rt);
break;
+ case OPC_LX_DSP:
+ op2 = MASK_LX(ctx->opcode);
+ switch (op2) {
+ case OPC_LBUX:
+ {
+ TCGv addr = tcg_temp_new();
+
+ save_cpu_state(ctx, 1);
+ gen_op_addr_add(ctx, addr, cpu_gpr[rs], cpu_gpr[rt]);
+ op_ld_lbu(cpu_gpr[rd], addr, ctx);
+ tcg_temp_free_i32(addr);
+ break;
+ }
+ case OPC_LHX:
+ {
+ TCGv addr = tcg_temp_new();
+
+ save_cpu_state(ctx, 1);
+ gen_op_addr_add(ctx, addr, cpu_gpr[rs], cpu_gpr[rt]);
+ op_ld_lh(cpu_gpr[rd], addr, ctx);
+ tcg_temp_free_i32(addr);
+ break;
+ }
+ case OPC_LWX:
+ {
+ TCGv addr = tcg_temp_new();
+
+ save_cpu_state(ctx, 1);
+ gen_op_addr_add(ctx, addr, cpu_gpr[rs], cpu_gpr[rt]);
+ op_ld_lw(cpu_gpr[rd], addr, ctx);
+ tcg_temp_free_i32(addr);
+ break;
+ }
+ }
+ break;
#if defined(TARGET_MIPS64)
case OPC_DEXTM ... OPC_DEXT:
case OPC_DINSM ... OPC_DINS:
--
1.7.5.4
- [Qemu-devel] [PATCH V4 00/11] Qemu MIPS ASE DSP Sup port, Jia Liu, 2012/03/29
- [Qemu-devel] [PATCH V4 01/11] Add MIPS DSP internal functions, Jia Liu, 2012/03/29
- [Qemu-devel] [PATCH V4 02/11] Use correct acc value to index cpu_HI/cpu_LO rather than using a fix number, Jia Liu, 2012/03/29
- [Qemu-devel] [PATCH V4 03/11] Add MIPS DSP Branch instruction Support, Jia Liu, 2012/03/29
- [Qemu-devel] [PATCH V4 04/11] Add MIPS DSP Load instructions Support,
Jia Liu <=
- [Qemu-devel] [PATCH V4 05/11] Add MIPS DSP Arithmetic instructions Support, Jia Liu, 2012/03/29
- [Qemu-devel] [PATCH V4 06/11] Add MIPS DSP GPR-Based Shift instructions Support, Jia Liu, 2012/03/29
- [Qemu-devel] [PATCH V4 07/11] Add MIPS DSP Multiply instructions Support, Jia Liu, 2012/03/29
- [Qemu-devel] [PATCH V4 08/11] Add MIPS DSP Bit/Manipulation instructions Support, Jia Liu, 2012/03/29
- [Qemu-devel] [PATCH V4 09/11] Add MIPS DSP Compare-Pick instructions Support, Jia Liu, 2012/03/29
- [Qemu-devel] [PATCH V4 10/11] Add MIPS DSP Accumulator and DSPControl Access instructions Support, Jia Liu, 2012/03/29
- [Qemu-devel] [PATCH V4 11/11] Add MIPS DSP Testcases, Jia Liu, 2012/03/30