[Top][All Lists]
[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]
Re: [Qemu-devel] [PATCH RFC v4 03/20] target-arm: Embed CPUARMState in Q
From: |
Andreas Färber |
Subject: |
Re: [Qemu-devel] [PATCH RFC v4 03/20] target-arm: Embed CPUARMState in QOM ARMCPU |
Date: |
Wed, 14 Mar 2012 23:30:24 +0100 |
User-agent: |
Mozilla/5.0 (X11; Linux x86_64; rv:10.0.2) Gecko/20120215 Thunderbird/10.0.2 |
Am 13.03.2012 14:18, schrieb Paolo Bonzini:
> Il 10/03/2012 17:53, Andreas Färber ha scritto:
>> /**
>> * ARMCPU:
>> + * @env: Legacy CPU state.
>> *
>> * An ARM CPU core.
>> */
>> @@ -58,7 +60,17 @@ typedef struct ARMCPU {
>> /*< private >*/
>> CPUState parent_obj;
>> /*< public >*/
>> +
>> + /* TODO Inline this and split off common state */
>> + CPUARMState env;
>> } ARMCPU;
>>
>
> As usual I don't like "legacy". :)
Well, it refers to "former CPUState of which some or many fields are
going to be extracted". I wouldn't want to write it into documentation
as such.
" * @env: CPUARMState" is not telling either.
Better wordings anyone?
> A more interesting distinction is
> between state that is relevant to the emulation, and state that is
> relevant to the main loop or the machine. The former is reinitialized
> after reset and can remain in CPUFooState. The latter is not
> reinitialized after reset, can move to QOM, and in most cases that's
> what we access when we use CPUArchState.
Actually I was planning on keeping CPU*State only for TCG fields.
Whether a field is reset or not should be determined by the reset
callback, not by a semi-magic memset() up to a certain field name.
That's especially problematic for cp15.
The CPU*State struct stays around for two reasons,
1) allowing an incremental conversion of targets,
2) allowing offset calculations for TCG from the middle of the struct.
Mentioning this, we need to review all my *CPU structs to make sure env
is the *first* member and that any fields accessed by offset in its
parent CPUState are placed *last*, to minimize the immediates, as
previously pointed out by rth. Starts to matter once we move icount into
CPUState, as done on qom-cpu-wip branch.
> Also, I understand that the conversion is not fully mechanical, but
> perhaps it can be made "more" mechanical than this? Splitting this
> patch in two would be nice, but I can't say I read it fully.
Hm, this patch has been around since v1 and so far nobody requested a
particular split... it would be possible to move init and reset code in
separate patches if deemed necessary? Peter?
Andreas
--
SUSE LINUX Products GmbH, Maxfeldstr. 5, 90409 Nürnberg, Germany
GF: Jeff Hawn, Jennifer Guild, Felix Imendörffer; HRB 16746 AG Nürnberg
[Qemu-devel] [PATCH RFC v4 00/20] QOM'ify ARM CPU, Andreas Färber, 2012/03/10
[Qemu-devel] [PATCH RFC v4 13/20] target-arm: Store VFP FPSID register in ARMCPUClass, Andreas Färber, 2012/03/10
[Qemu-devel] [PATCH RFC v4 07/20] target-arm: No longer abort on unhandled CPUIDs on reset, Andreas Färber, 2012/03/10
[Qemu-devel] [PATCH RFC v4 10/20] target-arm: Store SCTLR in ARMCPUClass, Andreas Färber, 2012/03/10
[Qemu-devel] [PATCH RFC v4 09/20] target-arm: Store CTR in ARMCPUClass, Andreas Färber, 2012/03/10
[Qemu-devel] [PATCH RFC v4 18/20] target-arm: Add cpuid-{variant, revision} properties to CPU, Andreas Färber, 2012/03/10
[Qemu-devel] [PATCH RFC v4 19/20] target-arm: Simplify pxa270 CPU classes, Andreas Färber, 2012/03/10
[Qemu-devel] [PATCH RFC v4 17/20] target-arm: Kill off cpu_reset_model_id(), Andreas Färber, 2012/03/10
[Qemu-devel] [PATCH RFC v4 15/20] target-arm: Store CLIDR in ARMCPUClass, Andreas Färber, 2012/03/10
[Qemu-devel] [PATCH RFC v4 20/20] hw/integratorcp: Add child property for CPU, Andreas Färber, 2012/03/10