Re: [Qemu-devel] [PATCH] pci: fix bridge IO/BASE

[Blue Swirl]

On Sun, Mar 4, 2012 at 22:29, Michael S. Tsirkin <address@hidden> wrote:
> On Sun, Mar 04, 2012 at 09:54:02PM +0000, Blue Swirl wrote:
>> >> 19.3.1.10 tells that the header type is 0, as you noted too. Still,
>> >> the register layout matches bridge spec instead, for example there are
>> >> bus number registers in place of BAR 2.
>> >
>> > Sorry I don't see this in 19.3.1
>> > Where are these registers documented?
>> > In my spec all registers from 0x10 on are greyed out which
>> > it says above means 'not implemented'?
>> > My spec also says 'Base Address' for 0x10 - 0x27.
>> >
>> > I see bus number and subordinate bus number
>> > registers at 0x40 and 0x41, this is outside
>> > the configuration header. The spec also says
>> > they are unused.
>>
>> Oh, I somehow read that they were in bridge locations 0x18 and 0x19.
>> Perhaps the is_bridge property should be removed after OpenBIOS no
>> longer wants to write to the registers.
>
> So we are in agreement then?
> The device seems to (more or less) go by the spec,

QEMU is correct here as is your original commit. The only change
(beside bug fixes for the problems you found, thanks) should be for
is_bridge.

> but openbios gets confused, apparently by the absence of BARs.
>
> Can you try debugging openbios to see what is wrong?

On second thought, I think 32 bit I/O was confusing OpenBIOS, probably
the host bridge device not so much. PCI handling in OpenBIOS should be
fixed.

> --
> MST