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Re: [Qemu-devel] [SeaBIOS] [Seabios] [PATCH 0/6] 64bit PCI BARs allocati
From: |
Gerd Hoffmann |
Subject: |
Re: [Qemu-devel] [SeaBIOS] [Seabios] [PATCH 0/6] 64bit PCI BARs allocations (take 2) |
Date: |
Mon, 05 Mar 2012 10:53:25 +0100 |
User-agent: |
Mozilla/5.0 (X11; Linux x86_64; rv:10.0.1) Gecko/20120216 Thunderbird/10.0.1 |
Hi,
> Hrmm. By my count, this would be the third "rewrite" of the PCI bar
> initialization in the last 14 months.
Indeed.
> Given the churn in this area, I don't want to commit patches that do
> wholesale code replacement. I'd prefer to see each patch
> independently add some functionality and perform its related cleanup.
Hardly doable, the algorithms are very different.
> Also, since Gerd has some patches pending in this area, we should
> figure out which direction makes sense. Can you explain on how this
> 64bit support is different from the support proposed by Gerd?
My code keeps all state needed to do the pci bar allocation in the
pci_bus struct. It counts how many bars of each type+size it has, then
uses this for the allocation. It doesn't need per-device state. The
logic is a bit twisted because of that. Main reason for this is that I
wrote it before "struct pci_device" showed up in seabios (although the
merge was afterwards).
Alexey's code takes a very different route: It uses pci_device data
structure instead and organizes the pci bars in per-region lists. It
makes sense to do that, I think that version is easier to understand
when you look at it the first time.
Both approaches will work fine in the end. I don't care much, I just
want something that works. It's probably a bit risky to merge Alexey's
version before the planned mid-march release.
cheers,
Gerd
- [Qemu-devel] [PATCH 6/6] 64bit PCI range in _CRS table, (continued)
Re: [Qemu-devel] [Seabios] [PATCH 0/6] 64bit PCI BARs allocations (take 2), Kevin O'Connor, 2012/03/04