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Re: [Qemu-devel] [PATCH] pci: fix bridge IO/BASE


From: Michael S. Tsirkin
Subject: Re: [Qemu-devel] [PATCH] pci: fix bridge IO/BASE
Date: Sun, 4 Mar 2012 21:27:17 +0200
User-agent: Mutt/1.5.21 (2010-09-15)

On Sun, Mar 04, 2012 at 05:49:04PM +0000, Blue Swirl wrote:
> On Sun, Mar 4, 2012 at 16:42, Michael S. Tsirkin <address@hidden> wrote:
> > On Sun, Mar 04, 2012 at 02:26:13PM +0000, Blue Swirl wrote:
> >> > It seems to have to do with the host bridge.
> >> > It's unusual to have host bridge present itself
> >> > as a pci to pci bridge but there it is.
> >>
> >> It looks like the I/O base calculations in OpenBIOS are confused
> >
> > Where's the source for that, BTW? Have build instructions?
> 
> Under roms/openbios or www.openbios.org. You need xsltproc.
> ../config/scripts/switch-arch sparc64
> make build-verbose
> qemu-system-sparc64 -bios obj-sparc64/openbios-builtin.elf.nostrip

I don't see anything obviously wrong in there, but
the behaviour does seem to indicate some firmware bug ...
I don't have the right toolchain - care debugging?

> >> by
> >> host bridge, after that all BARs are wrong. OpenBIOS also thinks that
> >> the host bridge is a device and attempts to configure six BARs instead
> >> of two.
> >
> > According to the spec it is a device, so should be ok?
> > If I just make BAR4 writeable we get past the
> > bios screen at least.
> > Maybe openbios gets confused if a device has no BARs?
> > Do things work for you with the patch below?
> > All it does is make BAR4 writeable, accesses go nowhere.
> 
> Looking at serial console, there is no crash, but VGA still does not work.

What do info pci/ifo mtree show now?

> >
> >
> > diff --git a/hw/apb_pci.c b/hw/apb_pci.c
> > index 1d25da8..fae841f 100644
> > --- a/hw/apb_pci.c
> > +++ b/hw/apb_pci.c
> > @@ -433,6 +433,7 @@ static int pbm_pci_host_init(PCIDevice *d)
> >     pci_set_word(d->config + PCI_STATUS,
> >                  PCI_STATUS_FAST_BACK | PCI_STATUS_66MHZ |
> >                  PCI_STATUS_DEVSEL_MEDIUM);
> > +    pci_set_long(d->wmask + 0x20, 0xfffffff0);
> >     return 0;
> >  }
> >
> > @@ -444,7 +445,6 @@ static void pbm_pci_host_class_init(ObjectClass *klass, 
> > void *data)
> >     k->vendor_id = PCI_VENDOR_ID_SUN;
> >     k->device_id = PCI_DEVICE_ID_SUN_SABRE;
> >     k->class_id = PCI_CLASS_BRIDGE_HOST;
> > -    k->is_bridge = 1;
> >  }
> >
> >  static TypeInfo pbm_pci_host_info = {
> > --
> > MST



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