Re: [Qemu-devel] How QEMU handle precise exception?

[Blue Swirl]

On Wed, Feb 29, 2012 at 12:45, 陳韋任 <address@hidden> wrote:
> Hi all,
>
>  I would like to know how QEMU handle precise exception. Basically, QEMU need
> to maintain a well-defined guest architecture state (register + memory) before
> returning to the exception handler.
>
>  For the guest register, does QEMU save the guest registers (except guest pc)
> before every guest instruction which might raise exception?

There are different approaches. Most registers (for example EAX on
i386) in CPUState are kept in synch.

Actually guest PC is not updated after every instruction, only before
instructions that can cause exceptions and after each basic block. PC
can be also recomputed with "search PC" function.

Many targets implement lazy handling of condition codes (NZVC etc.),
so they need to be computed when they are accessed.

In many architectures, FPU is running more or less asynchronously to
the core, but in QEMU, FPU instructions are calculated immediately.

Corner cases (like STI on x86 or priority order of simultaneously
active exceptions) should be also handled correctly.

> For the guest memory,
> is it because how QEMU does (see below) so that guest memory is in a 
> consistent
> state when guest exception occured?
>
>  - Emulate guest "store" memory operations in the same order as in the 
> original
>    program order.
>
>  - Emulate all potentially trapping guest instructions in the same order with
>    respect to the guest store instructions.

Memory operations are not reordered in any way.

>
>  Thanks!
>
> Regards,
> chenwj
>
> --
> Wei-Ren Chen (陳韋任)
> Computer Systems Lab, Institute of Information Science,
> Academia Sinica, Taiwan (R.O.C.)
> Tel:886-2-2788-3799 #1667
> Homepage: http://people.cs.nctu.edu.tw/~chenwj
>