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[Qemu-devel] [PATCH RFC v3 18/21] target-arm: Store CCSIDRs in ARMCPUCla
From: |
Andreas Färber |
Subject: |
[Qemu-devel] [PATCH RFC v3 18/21] target-arm: Store CCSIDRs in ARMCPUClass |
Date: |
Fri, 3 Feb 2012 03:59:49 +0100 |
Signed-off-by: Andreas Färber <address@hidden>
Cc: Peter Maydell <address@hidden>
---
target-arm/cpu-core.h | 1 +
target-arm/cpu.c | 18 ++++++++++++++++++
target-arm/helper.c | 14 --------------
3 files changed, 19 insertions(+), 14 deletions(-)
diff --git a/target-arm/cpu-core.h b/target-arm/cpu-core.h
index 0ed92ce..a58e62b 100644
--- a/target-arm/cpu-core.h
+++ b/target-arm/cpu-core.h
@@ -44,6 +44,7 @@ typedef struct ARMCPUClass {
struct {
uint32_t c0_cpuid;
uint32_t c0_cachetype;
+ uint32_t c0_ccsid[16];
uint32_t c0_clid;
uint32_t c0_c1[8];
uint32_t c0_c2[8];
diff --git a/target-arm/cpu.c b/target-arm/cpu.c
index 8333ca4..8186a96 100644
--- a/target-arm/cpu.c
+++ b/target-arm/cpu.c
@@ -47,6 +47,8 @@ static void arm_cpu_reset(CPU *c)
/* TODO Move these into arm_cpu_initfn() once no longer zeroed above. */
env->cp15.c0_cachetype = cpu_class->cp15.c0_cachetype;
+ memcpy(env->cp15.c0_ccsid, cpu_class->cp15.c0_ccsid,
+ 16 * sizeof(uint32_t));
env->cp15.c0_clid = cpu_class->cp15.c0_clid;
memcpy(env->cp15.c0_c1, cpu_class->cp15.c0_c1, 8 * sizeof(uint32_t));
memcpy(env->cp15.c0_c2, cpu_class->cp15.c0_c2, 8 * sizeof(uint32_t));
@@ -173,6 +175,7 @@ typedef struct ARMCPUInfo {
const char *name;
uint32_t id;
uint32_t cp15_c0_cachetype;
+ uint32_t cp15_c0_ccsid[16];
uint32_t cp15_c0_clid;
uint32_t cp15_c0_c1[8];
uint32_t cp15_c0_c2[8];
@@ -363,6 +366,11 @@ static const ARMCPUInfo arm_cpus[] = {
.name = "cortex-a8",
.id = 0x410fc080,
.cp15_c0_cachetype = 0x82048004,
+ .cp15_c0_ccsid = {
+ 0xe007e01a, /* 16k L1 dcache. */
+ 0x2007e01a, /* 16k L1 icache. */
+ 0xf0000000, /* No L2 icache. */
+ },
.cp15_c0_clid = (1 << 27) | (2 << 24) | 3,
.cp15_c0_c1 = {
0x1031, 0x11, 0x400, 0,
@@ -384,6 +392,10 @@ static const ARMCPUInfo arm_cpus[] = {
.name = "cortex-a9",
.id = 0x410fc090,
.cp15_c0_cachetype = 0x80038003,
+ .cp15_c0_ccsid = {
+ 0xe00fe015, /* 16k L1 dcache. */
+ 0x200fe015, /* 16k L1 icache. */
+ },
.cp15_c0_clid = (1 << 27) | (1 << 24) | 3,
.cp15_c0_c1 = {
0x1031, 0x11, 0x000, 0,
@@ -411,6 +423,11 @@ static const ARMCPUInfo arm_cpus[] = {
.name = "cortex-a15",
.id = 0x412fc0f1,
.cp15_c0_cachetype = 0x8444c004,
+ .cp15_c0_ccsid = {
+ 0x701fe00a, /* 32K L1 dcache */
+ 0x201fe00a, /* 32K L1 icache */
+ 0x711fe07a, /* 4096K L2 unified cache */
+ },
.cp15_c0_clid = 0x0a200023,
.cp15_c0_c1 = {
0x00001131, 0x00011011, 0x02010555, 0x00000000,
@@ -543,6 +560,7 @@ static void arm_cpu_class_init(ObjectClass *klass, void
*data)
k->cp15.c0_cpuid = info->id;
k->cp15.c0_cachetype = info->cp15_c0_cachetype;
+ memcpy(k->cp15.c0_ccsid, info->cp15_c0_ccsid, 16 * sizeof(uint32_t));
k->cp15.c0_clid = info->cp15_c0_clid;
memcpy(k->cp15.c0_c1, info->cp15_c0_c1, 8 * sizeof(uint32_t));
memcpy(k->cp15.c0_c2, info->cp15_c0_c2, 8 * sizeof(uint32_t));
diff --git a/target-arm/helper.c b/target-arm/helper.c
index 6f2c9a0..6ecae15 100644
--- a/target-arm/helper.c
+++ b/target-arm/helper.c
@@ -13,20 +13,6 @@
static void cpu_reset_model_id(CPUARMState *env, uint32_t id)
{
switch (id) {
- case ARM_CPUID_CORTEXA8:
- env->cp15.c0_ccsid[0] = 0xe007e01a; /* 16k L1 dcache. */
- env->cp15.c0_ccsid[1] = 0x2007e01a; /* 16k L1 icache. */
- env->cp15.c0_ccsid[2] = 0xf0000000; /* No L2 icache. */
- break;
- case ARM_CPUID_CORTEXA9:
- env->cp15.c0_ccsid[0] = 0xe00fe015; /* 16k L1 dcache. */
- env->cp15.c0_ccsid[1] = 0x200fe015; /* 16k L1 icache. */
- break;
- case ARM_CPUID_CORTEXA15:
- env->cp15.c0_ccsid[0] = 0x701fe00a; /* 32K L1 dcache */
- env->cp15.c0_ccsid[1] = 0x201fe00a; /* 32K L1 icache */
- env->cp15.c0_ccsid[2] = 0x711fe07a; /* 4096K L2 unified cache */
- break;
case ARM_CPUID_TI915T:
case ARM_CPUID_TI925T:
env->cp15.c15_i_max = 0x000;
--
1.7.7
- Re: [Qemu-devel] [PATCH RFC v3 14/21] target-arm: Move the PXA270's iwMMXt reset to pxa270_reset(), (continued)
[Qemu-devel] [PATCH RFC v3 16/21] target-arm: Store VFP MVFR0 and MVFR1 in ARMCPUClass, Andreas Färber, 2012/02/02
[Qemu-devel] [FYI v3 21/21] target-arm: Just for testing!, Andreas Färber, 2012/02/02
[Qemu-devel] [PATCH RFC v3 10/21] target-arm: Store cp15 c0_c1 and c0_c2 in ARMCPUClass, Andreas Färber, 2012/02/02
[Qemu-devel] [PATCH RFC v3 15/21] target-arm: Store VFP FPSID register in ARMCPUClass, Andreas Färber, 2012/02/02
[Qemu-devel] [PATCH RFC v3 08/21] target-arm: Move CPU feature flags out of CPUState, Andreas Färber, 2012/02/02
[Qemu-devel] [PATCH RFC v3 18/21] target-arm: Store CCSIDRs in ARMCPUClass,
Andreas Färber <=
[Qemu-devel] [PATCH RFC v3 11/21] target-arm: Store cp15 c0_cachetype register in ARMCPUClass, Andreas Färber, 2012/02/02
[Qemu-devel] [PATCH RFC v3 12/21] target-arm: Move cp15 c1_sys register to ARMCPUClass, Andreas Färber, 2012/02/02
[Qemu-devel] [PATCH RFC v3 20/21] target-arm: Prepare halted property for CPU, Andreas Färber, 2012/02/02