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[Qemu-devel] [PATCH v6 16/18] kvm: x86: Add user space part for in-kerne
From: |
Jan Kiszka |
Subject: |
[Qemu-devel] [PATCH v6 16/18] kvm: x86: Add user space part for in-kernel i8259 |
Date: |
Fri, 13 Jan 2012 18:35:11 +0100 |
Introduce the alternative 'kvm-i8259' device model that exploits KVM
in-kernel acceleration.
The PIIX3 initialization code is furthermore extended by KVM specific
IRQ route setup. GSI injection differs in KVM mode from the user space
model. As we can dispatch ISA-range IRQs to both IOAPIC and PIC inside
the kernel, we do not need to inject them separately. This is reflected
by a KVM-specific GSI handler.
Signed-off-by: Jan Kiszka <address@hidden>
---
Makefile.target | 2 +-
hw/kvm/i8259.c | 173 +++++++++++++++++++++++++++++++++++++++++++++++++++++++
hw/pc.h | 1 +
hw/pc_piix.c | 50 +++++++++++++++-
4 files changed, 221 insertions(+), 5 deletions(-)
create mode 100644 hw/kvm/i8259.c
diff --git a/Makefile.target b/Makefile.target
index 5e5b5d1..f49f96e 100644
--- a/Makefile.target
+++ b/Makefile.target
@@ -228,7 +228,7 @@ obj-i386-y += vmport.o
obj-i386-y += device-hotplug.o pci-hotplug.o smbios.o wdt_ib700.o
obj-i386-y += debugcon.o multiboot.o
obj-i386-y += pc_piix.o
-obj-i386-$(CONFIG_KVM) += kvm/clock.o kvm/apic.o
+obj-i386-$(CONFIG_KVM) += kvm/clock.o kvm/apic.o kvm/i8259.o
obj-i386-$(CONFIG_SPICE) += qxl.o qxl-logger.o qxl-render.o
# shared objects
diff --git a/hw/kvm/i8259.c b/hw/kvm/i8259.c
new file mode 100644
index 0000000..dc05002
--- /dev/null
+++ b/hw/kvm/i8259.c
@@ -0,0 +1,173 @@
+/*
+ * KVM in-kernel PIC (i8259) support
+ *
+ * Copyright (c) 2011 Siemens AG
+ *
+ * Authors:
+ * Jan Kiszka <address@hidden>
+ *
+ * This work is licensed under the terms of the GNU GPL version 2.
+ * See the COPYING file in the top-level directory.
+ */
+#include "hw/i8259_internal.h"
+#include "hw/apic_internal.h"
+#include "kvm.h"
+
+typedef struct KVMPICState KVMPICState;
+
+struct KVMPICState {
+ PICCommonState pic;
+};
+
+static void kvm_pic_get(PICCommonState *s)
+{
+ struct kvm_irqchip chip;
+ struct kvm_pic_state *kpic;
+ int ret;
+
+ chip.chip_id = s->master ? KVM_IRQCHIP_PIC_MASTER : KVM_IRQCHIP_PIC_SLAVE;
+ ret = kvm_vm_ioctl(kvm_state, KVM_GET_IRQCHIP, &chip);
+ if (ret < 0) {
+ fprintf(stderr, "KVM_GET_IRQCHIP failed: %s\n", strerror(ret));
+ abort();
+ }
+
+ kpic = &chip.chip.pic;
+
+ s->last_irr = kpic->last_irr;
+ s->irr = kpic->irr;
+ s->imr = kpic->imr;
+ s->isr = kpic->isr;
+ s->priority_add = kpic->priority_add;
+ s->irq_base = kpic->irq_base;
+ s->read_reg_select = kpic->read_reg_select;
+ s->poll = kpic->poll;
+ s->special_mask = kpic->special_mask;
+ s->init_state = kpic->init_state;
+ s->auto_eoi = kpic->auto_eoi;
+ s->rotate_on_auto_eoi = kpic->rotate_on_auto_eoi;
+ s->special_fully_nested_mode = kpic->special_fully_nested_mode;
+ s->init4 = kpic->init4;
+ s->elcr = kpic->elcr;
+ s->elcr_mask = kpic->elcr_mask;
+}
+
+static void kvm_pic_put(PICCommonState *s)
+{
+ struct kvm_irqchip chip;
+ struct kvm_pic_state *kpic;
+ int ret;
+
+ chip.chip_id = s->master ? KVM_IRQCHIP_PIC_MASTER : KVM_IRQCHIP_PIC_SLAVE;
+
+ kpic = &chip.chip.pic;
+
+ kpic->last_irr = s->last_irr;
+ kpic->irr = s->irr;
+ kpic->imr = s->imr;
+ kpic->isr = s->isr;
+ kpic->priority_add = s->priority_add;
+ kpic->irq_base = s->irq_base;
+ kpic->read_reg_select = s->read_reg_select;
+ kpic->poll = s->poll;
+ kpic->special_mask = s->special_mask;
+ kpic->init_state = s->init_state;
+ kpic->auto_eoi = s->auto_eoi;
+ kpic->rotate_on_auto_eoi = s->rotate_on_auto_eoi;
+ kpic->special_fully_nested_mode = s->special_fully_nested_mode;
+ kpic->init4 = s->init4;
+ kpic->elcr = s->elcr;
+ kpic->elcr_mask = s->elcr_mask;
+
+ ret = kvm_vm_ioctl(kvm_state, KVM_SET_IRQCHIP, &chip);
+ if (ret < 0) {
+ fprintf(stderr, "KVM_GET_IRQCHIP failed: %s\n", strerror(ret));
+ abort();
+ }
+}
+
+static void kvm_pic_pre_save(void *opaque)
+{
+ KVMPICState *s = opaque;
+
+ kvm_pic_get(&s->pic);
+}
+
+static int kvm_pic_post_load(void *opaque, int version_id)
+{
+ KVMPICState *s = opaque;
+
+ kvm_pic_put(&s->pic);
+ return 0;
+}
+
+static void kvm_pic_reset(DeviceState *dev)
+{
+ PICCommonState *s = container_of(dev, PICCommonState, dev.qdev);
+
+ pic_reset_common(s);
+ s->elcr = 0;
+
+ kvm_pic_put(s);
+}
+
+static void kvm_pic_set_irq(void *opaque, int irq, int level)
+{
+ int delivered;
+
+ delivered = kvm_irqchip_set_irq(kvm_state, irq, level);
+ apic_report_irq_delivered(delivered);
+}
+
+static int kvm_pic_init(ISADevice *dev)
+{
+ KVMPICState *s = DO_UPCAST(KVMPICState, pic.dev, dev);
+
+ memory_region_init_reservation(&s->pic.base_io, "kvm-pic", 2);
+ memory_region_init_reservation(&s->pic.elcr_io, "kvm-elcr", 1);
+
+ pic_init_common(&s->pic);
+
+ return 0;
+}
+
+qemu_irq *kvm_i8259_init(ISABus *bus)
+{
+ i8259_init_chip("kvm-i8259", bus, true);
+ i8259_init_chip("kvm-i8259", bus, false);
+
+ return qemu_allocate_irqs(kvm_pic_set_irq, NULL, ISA_NUM_IRQS);
+}
+
+static const VMStateDescription vmstate_kvm_pic = {
+ .name = "i8259",
+ .version_id = PIC_VMSTATE_VERSION,
+ .minimum_version_id = 1,
+ .minimum_version_id_old = 1,
+ .pre_save = kvm_pic_pre_save,
+ .post_load = kvm_pic_post_load,
+ .fields = (VMStateField[]) {
+ VMSTATE_STRUCT(pic, KVMPICState, 0, vmstate_pic_common,
PICCommonState),
+ VMSTATE_END_OF_LIST()
+ }
+};
+
+static ISADeviceInfo kvm_i8259_info = {
+ .qdev.name = "kvm-i8259",
+ .qdev.size = sizeof(KVMPICState),
+ .qdev.vmsd = &vmstate_kvm_pic,
+ .qdev.reset = kvm_pic_reset,
+ .qdev.no_user = 1,
+ .init = kvm_pic_init,
+ .qdev.props = (Property[]) {
+ PIC_PROPERTIES_COMMON(KVMPICState, pic),
+ DEFINE_PROP_END_OF_LIST()
+ },
+};
+
+static void kvm_pic_register(void)
+{
+ isa_qdev_register(&kvm_i8259_info);
+}
+
+device_init(kvm_pic_register)
diff --git a/hw/pc.h b/hw/pc.h
index ece069a..5e913db 100644
--- a/hw/pc.h
+++ b/hw/pc.h
@@ -64,6 +64,7 @@ bool parallel_mm_init(MemoryRegion *address_space,
extern DeviceState *isa_pic;
qemu_irq *i8259_init(ISABus *bus, qemu_irq parent_irq);
+qemu_irq *kvm_i8259_init(ISABus *bus);
int pic_read_irq(DeviceState *d);
int pic_get_output(DeviceState *d);
void pic_info(Monitor *mon);
diff --git a/hw/pc_piix.c b/hw/pc_piix.c
index f44f00e..868f4a5 100644
--- a/hw/pc_piix.c
+++ b/hw/pc_piix.c
@@ -53,6 +53,40 @@ static const int ide_iobase[MAX_IDE_BUS] = { 0x1f0, 0x170 };
static const int ide_iobase2[MAX_IDE_BUS] = { 0x3f6, 0x376 };
static const int ide_irq[MAX_IDE_BUS] = { 14, 15 };
+static void kvm_piix3_setup_irq_routing(bool pci_enabled)
+{
+ KVMState *s = kvm_state;
+ int ret, i;
+
+ if (kvm_check_extension(s, KVM_CAP_IRQ_ROUTING)) {
+ for (i = 0; i < 8; ++i) {
+ if (i == 2) {
+ continue;
+ }
+ kvm_irqchip_add_route(s, i, KVM_IRQCHIP_PIC_MASTER, i);
+ }
+ for (i = 8; i < 16; ++i) {
+ kvm_irqchip_add_route(s, i, KVM_IRQCHIP_PIC_SLAVE, i - 8);
+ }
+ ret = kvm_irqchip_commit_routes(s);
+ if (ret < 0) {
+ hw_error("KVM IRQ routing setup failed");
+ }
+ }
+}
+
+static void kvm_piix3_gsi_handler(void *opaque, int n, int level)
+{
+ GSIState *s = opaque;
+
+ if (n < ISA_NUM_IRQS) {
+ /* Kernel will forward to both PIC and IOAPIC */
+ qemu_set_irq(s->i8259_irq[n], level);
+ } else {
+ qemu_set_irq(s->ioapic_irq[n], level);
+ }
+}
+
static void ioapic_init(GSIState *gsi_state)
{
DeviceState *dev;
@@ -134,7 +168,13 @@ static void pc_init1(MemoryRegion *system_memory,
}
gsi_state = g_malloc0(sizeof(*gsi_state));
- gsi = qemu_allocate_irqs(gsi_handler, gsi_state, GSI_NUM_PINS);
+ if (kvm_enabled() && kvm_irqchip_in_kernel()) {
+ kvm_piix3_setup_irq_routing(pci_enabled);
+ gsi = qemu_allocate_irqs(kvm_piix3_gsi_handler, gsi_state,
+ GSI_NUM_PINS);
+ } else {
+ gsi = qemu_allocate_irqs(gsi_handler, gsi_state, GSI_NUM_PINS);
+ }
if (pci_enabled) {
pci_bus = i440fx_init(&i440fx_state, &piix3_devfn, &isa_bus, gsi,
@@ -154,11 +194,13 @@ static void pc_init1(MemoryRegion *system_memory,
}
isa_bus_irqs(isa_bus, gsi);
- if (!xen_enabled()) {
+ if (kvm_enabled() && kvm_irqchip_in_kernel()) {
+ i8259 = kvm_i8259_init(isa_bus);
+ } else if (xen_enabled()) {
+ i8259 = xen_interrupt_controller_init();
+ } else {
cpu_irq = pc_allocate_cpu_irq();
i8259 = i8259_init(isa_bus, cpu_irq[0]);
- } else {
- i8259 = xen_interrupt_controller_init();
}
for (i = 0; i < ISA_NUM_IRQS; i++) {
--
1.7.3.4
- [Qemu-devel] [PATCH v6 02/18] kvm: Move kvmclock into hw/kvm folder, (continued)
- [Qemu-devel] [PATCH v6 02/18] kvm: Move kvmclock into hw/kvm folder, Jan Kiszka, 2012/01/13
- [Qemu-devel] [PATCH v6 03/18] apic: Stop timer on reset, Jan Kiszka, 2012/01/13
- [Qemu-devel] [PATCH v6 13/18] kvm: Introduce core services for in-kernel irqchip support, Jan Kiszka, 2012/01/13
- [Qemu-devel] [PATCH v6 07/18] apic: Open-code timer save/restore, Jan Kiszka, 2012/01/13
- [Qemu-devel] [PATCH v6 14/18] kvm: x86: Establish IRQ0 override control, Jan Kiszka, 2012/01/13
- [Qemu-devel] [PATCH v6 12/18] memory: Introduce memory_region_init_reservation, Jan Kiszka, 2012/01/13
- [Qemu-devel] [PATCH v6 17/18] kvm: x86: Add user space part for in-kernel IOAPIC, Jan Kiszka, 2012/01/13
- [Qemu-devel] [PATCH v6 05/18] apic: Introduce apic_report_irq_delivered, Jan Kiszka, 2012/01/13
- [Qemu-devel] [PATCH v6 04/18] apic: Inject external NMI events via LINT1, Jan Kiszka, 2012/01/13
- [Qemu-devel] [PATCH v6 01/18] msi: Generalize msix_supported to msi_supported, Jan Kiszka, 2012/01/13
- [Qemu-devel] [PATCH v6 16/18] kvm: x86: Add user space part for in-kernel i8259,
Jan Kiszka <=
- [Qemu-devel] [PATCH v6 18/18] kvm: Arm in-kernel irqchip support, Jan Kiszka, 2012/01/13
- [Qemu-devel] [PATCH v6 15/18] kvm: x86: Add user space part for in-kernel APIC, Jan Kiszka, 2012/01/13
- [Qemu-devel] [PATCH v6 06/18] apic: Factor out base class for KVM reuse, Jan Kiszka, 2012/01/13
- [Qemu-devel] [PATCH v6 11/18] ioapic: Factor out base class for KVM reuse, Jan Kiszka, 2012/01/13