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[Qemu-devel] [PATCH v5 2/7] arm: Set frequencies for arm_timer
From: |
Mark Langsdorf |
Subject: |
[Qemu-devel] [PATCH v5 2/7] arm: Set frequencies for arm_timer |
Date: |
Thu, 29 Dec 2011 10:19:51 -0600 |
Use qdev properties to allow board modelers to set the frequencies
for the sp804 timer. Each of the sp804's timers can have an
individual frequency. The timers default to 1MHz.
Signed-off-by: Mark Langsdorf <address@hidden>
Reviewed-by: Peter Maydell <address@hidden>
Reviewed-by: Andreas Färber <address@hidden>
---
Changes from v3, v4
None
Changes from v2
Comment correctly describes behavior of properties
freqX variables are defined as uint32_t, not int
Changes from v1
Simplified multiple timer frequency handling
Removed the shared default
hw/arm_timer.c | 24 +++++++++++++++++++-----
1 files changed, 19 insertions(+), 5 deletions(-)
diff --git a/hw/arm_timer.c b/hw/arm_timer.c
index 0a5b9d2..60e1c63 100644
--- a/hw/arm_timer.c
+++ b/hw/arm_timer.c
@@ -9,6 +9,8 @@
#include "sysbus.h"
#include "qemu-timer.h"
+#include "qemu-common.h"
+#include "qdev.h"
/* Common timer implementation. */
@@ -178,6 +180,7 @@ typedef struct {
SysBusDevice busdev;
MemoryRegion iomem;
arm_timer_state *timer[2];
+ uint32_t freq0, freq1;
int level[2];
qemu_irq irq;
} sp804_state;
@@ -269,10 +272,11 @@ static int sp804_init(SysBusDevice *dev)
qi = qemu_allocate_irqs(sp804_set_irq, s, 2);
sysbus_init_irq(dev, &s->irq);
- /* ??? The timers are actually configurable between 32kHz and 1MHz, but
- we don't implement that. */
- s->timer[0] = arm_timer_init(1000000);
- s->timer[1] = arm_timer_init(1000000);
+ /* The timers are configurable between 32kHz and 1MHz
+ * defaulting to 1MHz but overrideable as individual properties */
+ s->timer[0] = arm_timer_init(s->freq0);
+ s->timer[1] = arm_timer_init(s->freq1);
+
s->timer[0]->irq = qi[0];
s->timer[1]->irq = qi[1];
memory_region_init_io(&s->iomem, &sp804_ops, s, "sp804", 0x1000);
@@ -281,6 +285,16 @@ static int sp804_init(SysBusDevice *dev)
return 0;
}
+static SysBusDeviceInfo sp804_info = {
+ .init = sp804_init,
+ .qdev.name = "sp804",
+ .qdev.size = sizeof(sp804_state),
+ .qdev.props = (Property[]) {
+ DEFINE_PROP_UINT32("freq0", sp804_state, freq0, 1000000),
+ DEFINE_PROP_UINT32("freq1", sp804_state, freq1, 1000000),
+ DEFINE_PROP_END_OF_LIST(),
+ }
+};
/* Integrator/CP timer module. */
@@ -349,7 +363,7 @@ static int icp_pit_init(SysBusDevice *dev)
static void arm_timer_register_devices(void)
{
sysbus_register_dev("integrator_pit", sizeof(icp_pit_state), icp_pit_init);
- sysbus_register_dev("sp804", sizeof(sp804_state), sp804_init);
+ sysbus_register_withprop(&sp804_info);
}
device_init(arm_timer_register_devices)
--
1.7.5.4
- [Qemu-devel] [PATCH v5 0/7] various ARM fixes for Calxeda Highbank, Mark Langsdorf, 2011/12/29
- [Qemu-devel] [PATCH v5 3/7] arm: add dummy v7 cp15 config_base_register, Mark Langsdorf, 2011/12/29
- [Qemu-devel] [PATCH v5 7/7] arm: make the number of GIC interrupts configurable, Mark Langsdorf, 2011/12/29
- [Qemu-devel] [PATCH v5 1/7] arm: add missing scu registers, Mark Langsdorf, 2011/12/29
- [Qemu-devel] [PATCH v5 4/7] arm: add dummy gic security registers, Mark Langsdorf, 2011/12/29
- [Qemu-devel] [PATCH v5 6/7] Add xgmac ethernet model, Mark Langsdorf, 2011/12/29
- [Qemu-devel] [PATCH v5 5/5] add L2x0/PL310 cache controller device, Mark Langsdorf, 2011/12/29
- [Qemu-devel] [PATCH v5 2/7] arm: Set frequencies for arm_timer,
Mark Langsdorf <=