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Re: [Qemu-devel] [PATCH] hw/pxa2xx.c: Fix handling of R/WC bits in PMCR
From: |
Peter Maydell |
Subject: |
Re: [Qemu-devel] [PATCH] hw/pxa2xx.c: Fix handling of R/WC bits in PMCR |
Date: |
Fri, 11 Nov 2011 23:20:53 +0000 |
On 11 November 2011 21:05, andrzej zaborowski <address@hidden> wrote:
>>> - s->pm_regs[addr>> 2]&= 0x15& ~(value& 0x2a);
>>> + /* Clear the write-one-to-clear bits... */
>>> + s->pm_regs[addr>> 2]&= ~(value& 0x2a);
>>> + /* ...and set the plain r/w bits */
>>> s->pm_regs[addr>> 2] |= value& 0x15;
>
> As I was about to push these patches also, I noticed this isn't
> exactly setting the r/w bits. But it would work if the first line was
> (~value) & 0x2a instead, should I fix it this way, am I looking at it
> right?
Rats, you're right. Your fix works (although it renders the comment wrong
as it's then not just clearing the W1C bits). Alternatively add an
extra line to give:
/* Clear the write-one-to-clear bits... */
s->pm_regs[addr >> 2] &= ~(value & 0x2a);
/* ...and set the plain r/w bits */
s->pm_regs[addr >> 2] &= ~0x15;
s->pm_regs[addr>> 2] |= value & 0x15;
(this is slightly different in effect from your code in that it
leaves register bits [31:5] untouched where yours will always clear
them.) Feel free to do whichever you think is clearest.
-- PMM