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[Qemu-devel] [PATCH 19/21] target-sparc: Implement FALIGNDATA inline.
From: |
Richard Henderson |
Subject: |
[Qemu-devel] [PATCH 19/21] target-sparc: Implement FALIGNDATA inline. |
Date: |
Tue, 18 Oct 2011 11:50:41 -0700 |
This is a relatively simple sequence of shifts.
Signed-off-by: Richard Henderson <address@hidden>
---
target-sparc/helper.h | 1 -
target-sparc/translate.c | 32 ++++++++++++++++++++++++++------
target-sparc/vis_helper.c | 12 ------------
3 files changed, 26 insertions(+), 19 deletions(-)
diff --git a/target-sparc/helper.h b/target-sparc/helper.h
index ec00436..7626504 100644
--- a/target-sparc/helper.h
+++ b/target-sparc/helper.h
@@ -125,7 +125,6 @@ DEF_HELPER_1(fqtoi, s32, env)
DEF_HELPER_2(fstox, s64, env, f32)
DEF_HELPER_2(fdtox, s64, env, f64)
DEF_HELPER_1(fqtox, s64, env)
-DEF_HELPER_3(faligndata, i64, env, i64, i64)
DEF_HELPER_FLAGS_2(fpmerge, TCG_CALL_CONST | TCG_CALL_PURE, i64, i64, i64)
DEF_HELPER_FLAGS_2(fmul8x16, TCG_CALL_CONST | TCG_CALL_PURE, i64, i64, i64)
diff --git a/target-sparc/translate.c b/target-sparc/translate.c
index 267ac71..591b391 100644
--- a/target-sparc/translate.c
+++ b/target-sparc/translate.c
@@ -2343,6 +2343,31 @@ static void gen_alignaddr(TCGv dst, TCGv s1, TCGv s2,
bool left)
tcg_temp_free(tmp);
}
+
+static void gen_faligndata(TCGv dst, TCGv gsr, TCGv s1, TCGv s2)
+{
+ TCGv t1, t2, shift;
+
+ t1 = tcg_temp_new();
+ t2 = tcg_temp_new();
+ shift = tcg_temp_new();
+
+ tcg_gen_andi_tl(shift, gsr, 7);
+ tcg_gen_shli_tl(shift, shift, 3);
+ tcg_gen_shl_tl(t1, s1, shift);
+
+ /* A shift of 64 does not produce 0 in TCG. Divide this into a
+ shift of (up to 63) followed by a constant shift of 1. */
+ tcg_gen_xori_tl(shift, shift, 63);
+ tcg_gen_shr_tl(t2, s2, shift);
+ tcg_gen_shri_tl(t2, t2, 1);
+
+ tcg_gen_or_tl(dst, t1, t2);
+
+ tcg_temp_free(t1);
+ tcg_temp_free(t2);
+ tcg_temp_free(shift);
+}
#endif
#define CHECK_IU_FEATURE(dc, FEATURE) \
@@ -4312,12 +4337,7 @@ static void disas_sparc_insn(DisasContext * dc, unsigned
int insn)
break;
case 0x048: /* VIS I faligndata */
CHECK_FPU_FEATURE(dc, VIS1);
- cpu_src1_64 = gen_load_fpr_D(dc, rs1);
- cpu_src2_64 = gen_load_fpr_D(dc, rs2);
- cpu_dst_64 = gen_dest_fpr_D();
- gen_helper_faligndata(cpu_dst_64, cpu_env,
- cpu_src1_64, cpu_src2_64);
- gen_store_fpr_D(dc, rd, cpu_dst_64);
+ gen_gsr_fop_DDD(dc, rd, rs1, rs2, gen_faligndata);
break;
case 0x04b: /* VIS I fpmerge */
CHECK_FPU_FEATURE(dc, VIS1);
diff --git a/target-sparc/vis_helper.c b/target-sparc/vis_helper.c
index 7830120..a992c29 100644
--- a/target-sparc/vis_helper.c
+++ b/target-sparc/vis_helper.c
@@ -41,18 +41,6 @@ target_ulong helper_array8(target_ulong pixel_addr,
target_ulong cubesize)
GET_FIELD_SP(pixel_addr, 11, 12);
}
-uint64_t helper_faligndata(CPUState *env, uint64_t src1, uint64_t src2)
-{
- uint64_t tmp;
-
- tmp = src1 << ((env->gsr & 7) * 8);
- /* on many architectures a shift of 64 does nothing */
- if ((env->gsr & 7) != 0) {
- tmp |= src2 >> (64 - (env->gsr & 7) * 8);
- }
- return tmp;
-}
-
#ifdef HOST_WORDS_BIGENDIAN
#define VIS_B64(n) b[7 - (n)]
#define VIS_W64(n) w[3 - (n)]
--
1.7.6.4
- [Qemu-devel] [PATCH 10/21] tcg: Optimize some forms of deposit., (continued)
- [Qemu-devel] [PATCH 10/21] tcg: Optimize some forms of deposit., Richard Henderson, 2011/10/18
- [Qemu-devel] [PATCH 08/21] target-sparc: Undo cpu_fpr rename., Richard Henderson, 2011/10/18
- [Qemu-devel] [PATCH 20/21] sparc-linux-user: Add some missing syscall numbers, Richard Henderson, 2011/10/18
- [Qemu-devel] [PATCH 07/21] target-sparc: Extract float128 move to a function., Richard Henderson, 2011/10/18
- [Qemu-devel] [PATCH 21/21] sparc-linux-user: Enable NPTL, Richard Henderson, 2011/10/18
- [Qemu-devel] [PATCH 03/21] target-sparc: Add accessors for double-precision fpr access., Richard Henderson, 2011/10/18
- [Qemu-devel] [PATCH 18/21] target-sparc: Tidy fpack32., Richard Henderson, 2011/10/18
- [Qemu-devel] [PATCH 16/21] target-sparc: Implement ALIGNADDR* inline., Richard Henderson, 2011/10/18
- [Qemu-devel] [PATCH 19/21] target-sparc: Implement FALIGNDATA inline.,
Richard Henderson <=
- Re: [Qemu-devel] [PATCH 00/21] Sparc FPU/VIS improvements, Blue Swirl, 2011/10/18
- [Qemu-devel] [PATCH 17/21] target-sparc: Implement BMASK/BSHUFFLE., Richard Henderson, 2011/10/18