Re: [Qemu-devel] [PATCH 11/22] i8259: Update IRQ state after reset

[Blue Swirl]

On Sun, Oct 2, 2011 at 7:47 PM, Avi Kivity <address@hidden> wrote:
>> >> For example, outputs A and B should both be driven high by reset.
>> >> They
>> >> are connected to a XNOR gate, whose output is fed to edge
>> >> triggered
>> >> device. The device should not see any edges outside of the reset
>> >> cycle, during reset cycle they are ignored.
>> >>
>> >
>> > I don't see the issue?  After phase 1 the two outputs will be high,
>> > after phase two they will be whatever the device logic computes.
>> >
>> > During phase 1 you may see an edge, but that also happens with real
>> > hardware.  The target device my see A and B driven high before it
>> > sees the reset pulse, and A and B (and the inputs of the XNOR
>> > gate) may have different timings.
>> >
>> > The device may see an edge immediately before reset, but then it
>> > will be reset itself.
>>
>> The difference is that on real HW the edge will happen when the reset
>> line is still active, so it will be ignored.
>>
>
> There is no way to guarantee this.  If A is driven high before the target 
> device detects RESET, it will see the edge.

That case is not what we have here, it would be equivalent of pulsing
qemu_irq reset lines for each device in order. This would be even
worse than what we have now.

> Of course real hardware has timing specs, but these are maximum latencies.  
> If the XNOR gate is especially fast today it can overtake the target device's 
> reset edge detector.

Devices don't have reset edge detectors.