Re: [Qemu-devel] [PATCH 0/5] target-arm: Implement UDIV/SDIV and fused multiply-accumulate

[Peter Maydell]

On 28 September 2011 20:13, Blue Swirl <address@hidden> wrote:
> On Wed, Sep 28, 2011 at 5:27 PM, Peter Maydell <address@hidden> wrote:
>> I've provided the PPC implementation
>> of the NaN-selection function because the architecture manual was
>> helpfully clear about what it was. x86 and SPARC don't seem to
>> document the behaviour in this area :-(
>
> SPARC64 VII Extensions says this:
> "Also fnmadd and fnmsub behavior with rs1=NaN or rs2=NaN is different between
> SPARC64 V and SPARC64 VII. SPARC64 VII outputs one of the NaN inputs
> as it is, while
> SPARC64 V outputs the one with the sign bit inverted."

To implement the NaN-selection you need to know more than
this -- specifically, if more than one input is a NaN,
then which NaN is returned? In the (inf * 0) + QNaN case,
do we return the input QNaN or something else? Is Invalid
set in that case? (IIRC SPARC does document this for the
two-operand ops, so it may just be that I didn't find the
equivalent bit for the three-operand ops.)

The distinction noted between the SPARC64 V and VII cases there
corresponds to whether the instruction should be implemented
with one of the float_muladd_negate_* flags, or with a
separate call to float*_chs().

I'm happy to leave this to whoever decides to implement these
insns for SPARC, though; my main concern was to make the
softfloat functions general enough to handle more than just
one architecture.

-- PMM