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[Qemu-devel] [PATCH 07/58] PPC: Fix IPI support in MPIC
From: |
Alexander Graf |
Subject: |
[Qemu-devel] [PATCH 07/58] PPC: Fix IPI support in MPIC |
Date: |
Wed, 14 Sep 2011 10:42:31 +0200 |
The current IPI support in the MPIC code is incomplete and doesn't work. This
code adds proper support for IPIs in MPIC by using the IDE register to remember
which CPUs IPIs are still outstanding to. New triggers through the IPI trigger
register only add to the list of CPUs we want to IPI.
Signed-off-by: Alexander Graf <address@hidden>
---
v1 -> v2:
- Use MAX_IPI instead of hardcoded 4
Signed-off-by: Alexander Graf <address@hidden>
---
hw/openpic.c | 17 +++++++++++++++--
1 files changed, 15 insertions(+), 2 deletions(-)
diff --git a/hw/openpic.c b/hw/openpic.c
index f7d5583..9710ac0 100644
--- a/hw/openpic.c
+++ b/hw/openpic.c
@@ -57,7 +57,7 @@
#define MAX_MBX 4
#define MAX_TMR 4
#define VECTOR_BITS 8
-#define MAX_IPI 0
+#define MAX_IPI 4
#define VID (0x00000000)
@@ -840,7 +840,9 @@ static void openpic_cpu_write_internal(void *opaque,
target_phys_addr_t addr,
case 0x60:
case 0x70:
idx = (addr - 0x40) >> 4;
- write_IRQreg(opp, opp->irq_ipi0 + idx, IRQ_IDE, val);
+ /* we use IDE as mask which CPUs to deliver the IPI to still. */
+ write_IRQreg(opp, opp->irq_ipi0 + idx, IRQ_IDE,
+ opp->src[opp->irq_ipi0 + idx].ide | val);
openpic_set_irq(opp, opp->irq_ipi0 + idx, 1);
openpic_set_irq(opp, opp->irq_ipi0 + idx, 0);
break;
@@ -934,6 +936,17 @@ static uint32_t openpic_cpu_read_internal(void *opaque,
target_phys_addr_t addr,
reset_bit(&src->ipvp, IPVP_ACTIVITY);
src->pending = 0;
}
+
+ if ((n_IRQ >= opp->irq_ipi0) && (n_IRQ < (opp->irq_ipi0 +
MAX_IPI))) {
+ src->ide &= ~(1 << idx);
+ if (src->ide && !test_bit(&src->ipvp, IPVP_SENSE)) {
+ /* trigger on CPUs that didn't know about it yet */
+ openpic_set_irq(opp, n_IRQ, 1);
+ openpic_set_irq(opp, n_IRQ, 0);
+ /* if all CPUs knew about it, set active bit again */
+ set_bit(&src->ipvp, IPVP_ACTIVITY);
+ }
+ }
}
break;
case 0xB0: /* PEOI */
--
1.6.0.2
- Re: [Qemu-devel] [PATCH 33/58] KVM: update kernel headers, (continued)
[Qemu-devel] [PATCH 19/58] PPC: bamboo: Use kvm api for freq and clock frequencies, Alexander Graf, 2011/09/14
[Qemu-devel] [PATCH 16/58] PPC: KVM: Add generic function to read host clockfreq, Alexander Graf, 2011/09/14
[Qemu-devel] [PATCH 46/58] ppc: booke206: use MAV=2.0 TSIZE definition, fix 4G pages, Alexander Graf, 2011/09/14
[Qemu-devel] [PATCH 23/58] PPC: E500: Remove unneeded CPU nodes, Alexander Graf, 2011/09/14
[Qemu-devel] [PATCH 13/58] PPC: E500: Generate IRQ lines for many CPUs, Alexander Graf, 2011/09/14
[Qemu-devel] [PATCH 10/58] PPC: MPIC: Fix CI bit definitions, Alexander Graf, 2011/09/14
[Qemu-devel] [PATCH 07/58] PPC: Fix IPI support in MPIC,
Alexander Graf <=
[Qemu-devel] [PATCH 31/58] PPC: E500: Bump CPU count to 15, Alexander Graf, 2011/09/14
[Qemu-devel] [PATCH 25/58] PPC: E500: Update cpu-release-addr property in cpu nodes, Alexander Graf, 2011/09/14
[Qemu-devel] [PATCH 27/58] device tree: dont fail operations, Alexander Graf, 2011/09/14
[Qemu-devel] [PATCH 28/58] device tree: give dt more size, Alexander Graf, 2011/09/14
[Qemu-devel] [PATCH 35/58] PPC: SPAPR: Use KVM function for time info, Alexander Graf, 2011/09/14