Re: [Qemu-devel] [PATCH 2/2] Qemu co-operation with kvm tsc deadline timer

[Liu, Jinsong]

Jan Kiszka wrote:
> On 2011-09-13 16:38, Liu, Jinsong wrote:
>> From c1b502d6548fcc41592cd90acc82109ee949df75 Mon Sep 17 00:00:00
>> 2001 
>> From: Liu, Jinsong <address@hidden>
>> Date: Tue, 13 Sep 2011 22:05:30 +0800
>> Subject: [PATCH] Qemu co-operation with kvm tsc deadline timer
>> 
>> KVM add emulation of lapic tsc deadline timer for guest.
>> This patch is co-operation work at qemu side.
>> 
>> Signed-off-by: Liu, Jinsong <address@hidden> ---
>>  target-i386/cpu.h |    2 ++
>>  target-i386/kvm.c |   14 ++++++++++++++
>>  2 files changed, 16 insertions(+), 0 deletions(-)
>> 
>> diff --git a/target-i386/cpu.h b/target-i386/cpu.h
>> index 935d08a..62ff73c 100644
>> --- a/target-i386/cpu.h
>> +++ b/target-i386/cpu.h
>> @@ -283,6 +283,7 @@
>>  #define MSR_IA32_APICBASE_BSP           (1<<8)
>>  #define MSR_IA32_APICBASE_ENABLE        (1<<11)
>>  #define MSR_IA32_APICBASE_BASE          (0xfffff<<12)
>> +#define MSR_IA32_TSCDEADLINE            0x6e0
>> 
>>  #define MSR_MTRRcap                 0xfe
>>  #define MSR_MTRRcap_VCNT            8
>> @@ -687,6 +688,7 @@ typedef struct CPUX86State {
>>      uint64_t async_pf_en_msr;
>> 
>>      uint64_t tsc;
>> +    uint64_t tsc_deadline;
> 
> This field has to be saved/restored for snapshots/migrations.
> 
> Frankly, I've no clue right now if substates are in vogue again (they
> had problems in their binary format) or if you can simply add a
> versioned top-level field and bump the CPUState version number.
> 

Yes, it would be saved/restored. After migration, tsc_deadline would be set to 
MSR_IA32_TSCDEADLINE to trigger tsc timer interrupt.

>> 
>>      uint64_t mcg_status;
>> 
>> diff --git a/target-i386/kvm.c b/target-i386/kvm.c
>> index aa843f0..206fcad 100644
>> --- a/target-i386/kvm.c
>> +++ b/target-i386/kvm.c
>> @@ -59,6 +59,7 @@ const KVMCapabilityInfo
>> kvm_arch_required_capabilities[] = { 
>> 
>>  static bool has_msr_star;
>>  static bool has_msr_hsave_pa;
>> +static bool has_msr_tsc_deadline;
>>  static bool has_msr_async_pf_en;
>>  static int lm_capable_kernel;
>> 
>> @@ -571,6 +572,10 @@ static int kvm_get_supported_msrs(KVMState *s)
>>                      has_msr_hsave_pa = true;
>>                      continue;
>>                  }
>> +                if (kvm_msr_list->indices[i] ==
>> MSR_IA32_TSCDEADLINE) { +                    has_msr_tsc_deadline =
>> true; +                    continue;
>> +                }
>>              }
>>          }
>> 
>> @@ -899,6 +904,9 @@ static int kvm_put_msrs(CPUState *env, int
>>          level)      if (has_msr_hsave_pa) {
>> kvm_msr_entry_set(&msrs[n++], MSR_VM_HSAVE_PA, env->vm_hsave);     
>> } +    if (has_msr_tsc_deadline) { +       
>>  kvm_msr_entry_set(&msrs[n++], MSR_IA32_TSCDEADLINE,
>>      env->tsc_deadline); +    } #ifdef TARGET_X86_64 if
>>          (lm_capable_kernel) { kvm_msr_entry_set(&msrs[n++],
>> MSR_CSTAR, env->cstar); @@ -1145,6 +1153,9 @@ static int
>>          kvm_get_msrs(CPUState *env)      if (has_msr_hsave_pa) {
>>      msrs[n++].index = MSR_VM_HSAVE_PA; }
>> +    if (has_msr_tsc_deadline) {
>> +        msrs[n++].index = MSR_IA32_TSCDEADLINE;
>> +    }
>> 
>>      if (!env->tsc_valid) {
>>          msrs[n++].index = MSR_IA32_TSC;
>> @@ -1213,6 +1224,9 @@ static int kvm_get_msrs(CPUState *env)        
>>              case MSR_IA32_TSC: env->tsc = msrs[i].data;
>>              break;
>> +        case MSR_IA32_TSCDEADLINE:
>> +            env->tsc_deadline = msrs[i].data;
>> +            break;
>>          case MSR_VM_HSAVE_PA:
>>              env->vm_hsave = msrs[i].data;
>>              break;
> 
> Just to double check: This feature is exposed to the guest when A) the
> host CPU supports it and B) QEMU passed down guest CPU specifications
> (cpuid data) that allow it as well?
> 
> Jan

Yes.

Thanks,
Jinsong