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[Qemu-devel] [PATCH 088/111] m68k: allows bfins to manage correctly widt
From: |
Bryce Lanham |
Subject: |
[Qemu-devel] [PATCH 088/111] m68k: allows bfins to manage correctly width = 32 |
Date: |
Wed, 17 Aug 2011 15:52:38 -0500 |
From: Laurent Vivier <address@hidden>
tcg_gen_shl_i32() doesn't manage a shift of 32.
As 32 >= width >= 1, we use two tcg_gen_shl_i32():
tcg_gen_shl_i32(1) and tcg_gen_shl_i32(width - 1)
seen with gcc testsuite,
gcc-4.1.2/gcc/testsuite/gcc.c-torture/execute/991118-1.c
Signed-off-by: Laurent Vivier <address@hidden>
---
target-m68k/translate.c | 6 +++++-
1 files changed, 5 insertions(+), 1 deletions(-)
diff --git a/target-m68k/translate.c b/target-m68k/translate.c
index 96ea93f..52df274 100644
--- a/target-m68k/translate.c
+++ b/target-m68k/translate.c
@@ -3215,7 +3215,11 @@ static void gen_bitfield_ins(TCGv offset, TCGv width,
TCGv src,
/* tmp = (1u << width) - 1; */
- tcg_gen_shl_i32(tmp, tcg_const_i32(1), width);
+ /* width is between 1 and 32
+ * tcg_gen_shl_i32() cannot manage value 32
+ */
+ tcg_gen_subi_i32(tmp, width, 1);
+ tcg_gen_shl_i32(tmp, tcg_const_i32(2), tmp);
tcg_gen_subi_i32(tmp, tmp, 1);
/* tmp = tmp & src; */
--
1.7.2.3
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