On Fri, May 20, 2011 at 5:46 PM, Anthony Liguori<address@hidden> wrote:
> On 05/20/2011 09:40 AM, Richard Henderson wrote:
>>
>> On 05/20/2011 07:31 AM, Anthony Liguori wrote:
>>>
>>> But is this a characteristic of devices or is this a characteristic of
>>> the chipset/CPU?
>>
>> Chipset.
>
> So if the chipset only allows accesses that are 64-bit, then you'll want to
> have hierarchical dispatch filter non 64-bit accesses and raise an MCE
> appropriately.
>
> So you don't need anything in MemoryRegion, you need code in the dispatch
> path.
Sparc (32/64) systems are also very picky about wrong sized accesses.
I think the buses have lines for access size and the device can (and
they will) signal an error in these cases. Then the bus controller
will raise an NMI.
I think the easiest way to handle this could be to use overlapping
registrations for specific sizes. Then we could make a default error
generator device, which would just signal NMI/MCE on any access. It
would register for all of the picky area with lowest possible
priority. Other devices would register the small working access areas
with no knowledge about this error generator device. Any correct
access should go to other devices, bad accesses to the error
generator.
Though this would not be very different from current unassigned access handling.