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Re: [Qemu-devel] [RFC 18/28] target-xtensa: implement exceptions
From: |
Richard Henderson |
Subject: |
Re: [Qemu-devel] [RFC 18/28] target-xtensa: implement exceptions |
Date: |
Wed, 04 May 2011 10:00:49 -0700 |
User-agent: |
Mozilla/5.0 (X11; U; Linux x86_64; en-US; rv:1.9.2.17) Gecko/20110428 Fedora/3.1.10-1.fc14 Thunderbird/3.1.10 |
On 05/04/2011 09:33 AM, Richard Henderson wrote:
> This is a case where you almost certainly want to check this
> condition inside QEMU and translate the opcode differently.
>
> See cpu_get_tb_cpu_state, which sets bits in *flags. These
> flags can then be checked in tb->flags while translating.
> At which point you'd avoid all the conditionalization on
> the value in PS here in check_privilege and merely issue
> the exception_cause.
>
> The ARM port is a good example for testing these sorts of bits.
Actually, while the tb flags are useful, privileged instructions
are usually checked by testing mmu_index, since we already have
to generate different code for the TB based on which TLB entry we
need to access.
r~
- Re: [Qemu-devel] [RFC 12/28] target-xtensa: implement shifts (ST1 and RST1 groups), (continued)
[Qemu-devel] [RFC 13/28] target-xtensa: implement LSAI group, Max Filippov, 2011/05/03
[Qemu-devel] [RFC 14/28] target-xtensa: mark reserved and TBD opcodes, Max Filippov, 2011/05/03
[Qemu-devel] [RFC 15/28] target-xtensa: big endian support, Max Filippov, 2011/05/03
[Qemu-devel] [RFC 16/28] target-xtensa: implement SYNC group, Max Filippov, 2011/05/03
[Qemu-devel] [RFC 17/28] target-xtensa: implement CACHE group, Max Filippov, 2011/05/03
[Qemu-devel] [RFC 18/28] target-xtensa: implement exceptions, Max Filippov, 2011/05/03
[Qemu-devel] [RFC 19/28] target-xtensa: implement RST2 group (32 bit mul/div/rem), Max Filippov, 2011/05/03
[Qemu-devel] [RFC 20/28] target-xtensa: implement windowed registers, Max Filippov, 2011/05/03