Re: [Qemu-devel] [RFC 11/28] target-xtensa: implement RST3 group

[Richard Henderson]

On 05/03/2011 05:59 PM, Max Filippov wrote:
> +            case 2: /*SEXTu*/
> +                HAS_OPTION(XTENSA_OPTION_MISC_OP);
> +                {
> +                    TCGv_i32 tmp = tcg_temp_new_i32();
> +                    tcg_gen_shli_i32(tmp, cpu_R[RRR_S], 24 - RRR_T);
> +                    tcg_gen_sari_i32(cpu_R[RRR_R], tmp, 24 - RRR_T);
> +                    tcg_temp_free(tmp);

It's probably worth special-casing extensions from bit 7 and 15
as normal 8 and 16-bit sign-extensions.  Those are likely to be
99% of all extension operations actually performed.


r~