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[Qemu-devel] [RFC 27/28] target-xtensa: implement CPENABLE and PRID SRs
From: |
Max Filippov |
Subject: |
[Qemu-devel] [RFC 27/28] target-xtensa: implement CPENABLE and PRID SRs |
Date: |
Wed, 4 May 2011 04:59:27 +0400 |
Signed-off-by: Max Filippov <address@hidden>
---
hw/xtensa_sample.c | 1 +
target-xtensa/cpu.h | 2 ++
target-xtensa/translate.c | 7 +++++++
3 files changed, 10 insertions(+), 0 deletions(-)
diff --git a/hw/xtensa_sample.c b/hw/xtensa_sample.c
index b1da7e1..797a0c4 100644
--- a/hw/xtensa_sample.c
+++ b/hw/xtensa_sample.c
@@ -18,6 +18,7 @@ static void xtensa_init(ram_addr_t ram_size,
fprintf(stderr, "Unable to find CPU definition\n");
exit(1);
}
+ env->sregs[PRID] = n;
}
ram_offset = qemu_ram_alloc(NULL, "xtensa.dram", 0x10000);
diff --git a/target-xtensa/cpu.h b/target-xtensa/cpu.h
index f3028a7..dbd3550 100644
--- a/target-xtensa/cpu.h
+++ b/target-xtensa/cpu.h
@@ -118,12 +118,14 @@ enum {
DEPC = 192,
EPS2 = 194,
EXCSAVE1 = 209,
+ CPENABLE = 224,
INTSET = 226,
INTCLEAR = 227,
INTENABLE = 228,
PS = 230,
EXCCAUSE = 232,
CCOUNT = 234,
+ PRID = 235,
EXCVADDR = 238,
CCOMPARE = 240,
};
diff --git a/target-xtensa/translate.c b/target-xtensa/translate.c
index 4df1b57..b72f1cf 100644
--- a/target-xtensa/translate.c
+++ b/target-xtensa/translate.c
@@ -88,12 +88,14 @@ static const char * const sregnames[256] = {
[EXCSAVE1 + 4] = "EXCSAVE5",
[EXCSAVE1 + 5] = "EXCSAVE6",
[EXCSAVE1 + 6] = "EXCSAVE7",
+ [CPENABLE] = "CPENABLE",
[INTSET] = "INTSET",
[INTCLEAR] = "INTCLEAR",
[INTENABLE] = "INTENABLE",
[PS] = "PS",
[EXCCAUSE] = "EXCCAUSE",
[CCOUNT] = "CCOUNT",
+ [PRID] = "PRID",
[EXCVADDR] = "EXCVADDR",
[CCOMPARE] = "CCOMPARE0",
[CCOMPARE + 1] = "CCOMPARE1",
@@ -192,6 +194,10 @@ static void gen_wsr_ps(DisasContext *dc, uint32_t sr,
TCGv_i32 v)
gen_check_interrupts(dc);
}
+static void gen_wsr_prid(DisasContext *dc, uint32_t sr, TCGv_i32 v)
+{
+}
+
static void gen_wsr_ccompare(DisasContext *dc, uint32_t sr, TCGv_i32 v)
{
TCGv_i32 id = tcg_const_i32(sr - CCOMPARE);
@@ -210,6 +216,7 @@ static void gen_wsr(DisasContext *dc, uint32_t sr, TCGv_i32
s)
[WINDOW_BASE] = gen_wsr_windowbase,
[WINDOW_START] = gen_wsr_windowstart,
[PS] = gen_wsr_ps,
+ [PRID] = gen_wsr_prid,
[CCOMPARE] = gen_wsr_ccompare,
[CCOMPARE + 1] = gen_wsr_ccompare,
[CCOMPARE + 2] = gen_wsr_ccompare,
--
1.7.3.4
- Re: [Qemu-devel] [RFC 20/28] target-xtensa: implement windowed registers, (continued)
[Qemu-devel] [RFC 21/28] target-xtensa: implement loop option, Max Filippov, 2011/05/03
[Qemu-devel] [RFC 22/28] target-xtensa: implement extended L32R, Max Filippov, 2011/05/03
[Qemu-devel] [RFC 23/28] target-xtensa: implement unaligned exception option, Max Filippov, 2011/05/03
[Qemu-devel] [RFC 24/28] target-xtensa: implement SIMCALL, Max Filippov, 2011/05/03
[Qemu-devel] [RFC 25/28] target-xtensa: implement interrupt option, Max Filippov, 2011/05/03
[Qemu-devel] [RFC 26/28] target-xtensa: implement accurate window check, Max Filippov, 2011/05/03
[Qemu-devel] [RFC 27/28] target-xtensa: implement CPENABLE and PRID SRs,
Max Filippov <=
[Qemu-devel] [RFC 28/28] target-xtensa: implement relocatable vectors, Max Filippov, 2011/05/03
Re: [Qemu-devel] [RFC 01/28] target-xtensa: add target stubs, Max Filippov, 2011/05/04
Re: [Qemu-devel] [RFC 01/28] target-xtensa: add target stubs, Blue Swirl, 2011/05/04