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Re: [Qemu-devel] [PATCH 1/4] softfloat: move all default NaN definitions
From: |
Aurelien Jarno |
Subject: |
Re: [Qemu-devel] [PATCH 1/4] softfloat: move all default NaN definitions to softfloat.h. |
Date: |
Sun, 20 Feb 2011 22:49:52 +0100 |
User-agent: |
Mutt/1.5.18 (2008-05-17) |
On Fri, Feb 18, 2011 at 03:49:14PM +0100, Christophe Lyon wrote:
> These special values are needed to implement some helper functions,
> which return/use these values in some cases.
>
> Signed-off-by: Christophe Lyon <address@hidden>
> ---
> fpu/softfloat-specialize.h | 68 -------------------------------------------
> fpu/softfloat.h | 69
> ++++++++++++++++++++++++++++++++++++++++++++
> 2 files changed, 69 insertions(+), 68 deletions(-)
>
> diff --git a/fpu/softfloat-specialize.h b/fpu/softfloat-specialize.h
> index 2d025bf..adc5ada 100644
> --- a/fpu/softfloat-specialize.h
> +++ b/fpu/softfloat-specialize.h
> @@ -30,12 +30,6 @@ these four paragraphs for those parts of this code that
> are retained.
>
>
> =============================================================================*/
>
> -#if defined(TARGET_MIPS) || defined(TARGET_SH4)
> -#define SNAN_BIT_IS_ONE 1
> -#else
> -#define SNAN_BIT_IS_ONE 0
> -#endif
> -
>
> /*----------------------------------------------------------------------------
> | Raises the exceptions specified by `flags'. Floating-point traps can be
> | defined here if desired. It is currently not possible for such a trap
> @@ -57,17 +51,6 @@ typedef struct {
> } commonNaNT;
>
>
> /*----------------------------------------------------------------------------
> -| The pattern for a default generated half-precision NaN.
> -*----------------------------------------------------------------------------*/
> -#if defined(TARGET_ARM)
> -#define float16_default_nan make_float16(0x7E00)
> -#elif SNAN_BIT_IS_ONE
> -#define float16_default_nan make_float16(0x7DFF)
> -#else
> -#define float16_default_nan make_float16(0xFE00)
> -#endif
> -
> -/*----------------------------------------------------------------------------
> | Returns 1 if the half-precision floating-point value `a' is a quiet
> | NaN; otherwise returns 0.
>
> *----------------------------------------------------------------------------*/
> @@ -158,19 +141,6 @@ static float16 commonNaNToFloat16(commonNaNT a
> STATUS_PARAM)
> }
>
>
> /*----------------------------------------------------------------------------
> -| The pattern for a default generated single-precision NaN.
> -*----------------------------------------------------------------------------*/
> -#if defined(TARGET_SPARC)
> -#define float32_default_nan make_float32(0x7FFFFFFF)
> -#elif defined(TARGET_PPC) || defined(TARGET_ARM) || defined(TARGET_ALPHA)
> -#define float32_default_nan make_float32(0x7FC00000)
> -#elif SNAN_BIT_IS_ONE
> -#define float32_default_nan make_float32(0x7FBFFFFF)
> -#else
> -#define float32_default_nan make_float32(0xFFC00000)
> -#endif
> -
> -/*----------------------------------------------------------------------------
> | Returns 1 if the single-precision floating-point value `a' is a quiet
> | NaN; otherwise returns 0.
>
> *----------------------------------------------------------------------------*/
> @@ -413,19 +383,6 @@ static float32 propagateFloat32NaN( float32 a, float32 b
> STATUS_PARAM)
> }
>
>
> /*----------------------------------------------------------------------------
> -| The pattern for a default generated double-precision NaN.
> -*----------------------------------------------------------------------------*/
> -#if defined(TARGET_SPARC)
> -#define float64_default_nan make_float64(LIT64( 0x7FFFFFFFFFFFFFFF ))
> -#elif defined(TARGET_PPC) || defined(TARGET_ARM) || defined(TARGET_ALPHA)
> -#define float64_default_nan make_float64(LIT64( 0x7FF8000000000000 ))
> -#elif SNAN_BIT_IS_ONE
> -#define float64_default_nan make_float64(LIT64( 0x7FF7FFFFFFFFFFFF ))
> -#else
> -#define float64_default_nan make_float64(LIT64( 0xFFF8000000000000 ))
> -#endif
> -
> -/*----------------------------------------------------------------------------
> | Returns 1 if the double-precision floating-point value `a' is a quiet
> | NaN; otherwise returns 0.
>
> *----------------------------------------------------------------------------*/
> @@ -564,19 +521,6 @@ static float64 propagateFloat64NaN( float64 a, float64 b
> STATUS_PARAM)
> #ifdef FLOATX80
>
>
> /*----------------------------------------------------------------------------
> -| The pattern for a default generated extended double-precision NaN. The
> -| `high' and `low' values hold the most- and least-significant bits,
> -| respectively.
> -*----------------------------------------------------------------------------*/
> -#if SNAN_BIT_IS_ONE
> -#define floatx80_default_nan_high 0x7FFF
> -#define floatx80_default_nan_low LIT64( 0xBFFFFFFFFFFFFFFF )
> -#else
> -#define floatx80_default_nan_high 0xFFFF
> -#define floatx80_default_nan_low LIT64( 0xC000000000000000 )
> -#endif
> -
> -/*----------------------------------------------------------------------------
> | Returns 1 if the extended double-precision floating-point value `a' is a
> | quiet NaN; otherwise returns 0. This slightly differs from the same
> | function for other types as floatx80 has an explicit bit.
> @@ -728,18 +672,6 @@ static floatx80 propagateFloatx80NaN( floatx80 a,
> floatx80 b STATUS_PARAM)
> #ifdef FLOAT128
>
>
> /*----------------------------------------------------------------------------
> -| The pattern for a default generated quadruple-precision NaN. The `high'
> and
> -| `low' values hold the most- and least-significant bits, respectively.
> -*----------------------------------------------------------------------------*/
> -#if SNAN_BIT_IS_ONE
> -#define float128_default_nan_high LIT64( 0x7FFF7FFFFFFFFFFF )
> -#define float128_default_nan_low LIT64( 0xFFFFFFFFFFFFFFFF )
> -#else
> -#define float128_default_nan_high LIT64( 0xFFFF800000000000 )
> -#define float128_default_nan_low LIT64( 0x0000000000000000 )
> -#endif
> -
> -/*----------------------------------------------------------------------------
> | Returns 1 if the quadruple-precision floating-point value `a' is a quiet
> | NaN; otherwise returns 0.
>
> *----------------------------------------------------------------------------*/
> diff --git a/fpu/softfloat.h b/fpu/softfloat.h
> index e57ee1e..f34a938 100644
> --- a/fpu/softfloat.h
> +++ b/fpu/softfloat.h
> @@ -77,6 +77,12 @@ typedef int64_t sbits64;
> #define LIT64( a ) a##LL
> #define INLINE static inline
>
> +#if defined(TARGET_MIPS) || defined(TARGET_SH4)
> +#define SNAN_BIT_IS_ONE 1
> +#else
> +#define SNAN_BIT_IS_ONE 0
> +#endif
> +
>
> /*----------------------------------------------------------------------------
> | The macro `FLOATX80' must be defined to enable the extended
> double-precision
> | floating-point format `floatx80'. If this macro is not defined, the
> @@ -278,6 +284,17 @@ int float16_is_signaling_nan( float16 );
> float16 float16_maybe_silence_nan( float16 );
>
>
> /*----------------------------------------------------------------------------
> +| The pattern for a default generated half-precision NaN.
> +*----------------------------------------------------------------------------*/
> +#if defined(TARGET_ARM)
> +#define float16_default_nan make_float16(0x7E00)
> +#elif SNAN_BIT_IS_ONE
> +#define float16_default_nan make_float16(0x7DFF)
> +#else
> +#define float16_default_nan make_float16(0xFE00)
> +#endif
> +
> +/*----------------------------------------------------------------------------
> | Software IEC/IEEE single-precision conversion routines.
>
> *----------------------------------------------------------------------------*/
> int float32_to_int16_round_to_zero( float32 STATUS_PARAM );
> @@ -366,6 +383,20 @@ INLINE int float32_is_zero_or_denormal(float32 a)
> #define float32_one make_float32(0x3f800000)
> #define float32_ln2 make_float32(0x3f317218)
>
> +
> +/*----------------------------------------------------------------------------
> +| The pattern for a default generated single-precision NaN.
> +*----------------------------------------------------------------------------*/
> +#if defined(TARGET_SPARC)
> +#define float32_default_nan make_float32(0x7FFFFFFF)
> +#elif defined(TARGET_PPC) || defined(TARGET_ARM) || defined(TARGET_ALPHA)
> +#define float32_default_nan make_float32(0x7FC00000)
> +#elif SNAN_BIT_IS_ONE
> +#define float32_default_nan make_float32(0x7FBFFFFF)
> +#else
> +#define float32_default_nan make_float32(0xFFC00000)
> +#endif
> +
>
> /*----------------------------------------------------------------------------
> | Software IEC/IEEE double-precision conversion routines.
>
> *----------------------------------------------------------------------------*/
> @@ -452,6 +483,19 @@ INLINE int float64_is_any_nan(float64 a)
> #define float64_one make_float64(0x3ff0000000000000LL)
> #define float64_ln2 make_float64(0x3fe62e42fefa39efLL)
>
> +/*----------------------------------------------------------------------------
> +| The pattern for a default generated double-precision NaN.
> +*----------------------------------------------------------------------------*/
> +#if defined(TARGET_SPARC)
> +#define float64_default_nan make_float64(LIT64( 0x7FFFFFFFFFFFFFFF ))
> +#elif defined(TARGET_PPC) || defined(TARGET_ARM) || defined(TARGET_ALPHA)
> +#define float64_default_nan make_float64(LIT64( 0x7FF8000000000000 ))
> +#elif SNAN_BIT_IS_ONE
> +#define float64_default_nan make_float64(LIT64( 0x7FF7FFFFFFFFFFFF ))
> +#else
> +#define float64_default_nan make_float64(LIT64( 0xFFF8000000000000 ))
> +#endif
> +
> #ifdef FLOATX80
>
>
> /*----------------------------------------------------------------------------
> @@ -520,6 +564,19 @@ INLINE int floatx80_is_any_nan(floatx80 a)
> return ((a.high & 0x7fff) == 0x7fff) && (a.low<<1);
> }
>
> +/*----------------------------------------------------------------------------
> +| The pattern for a default generated extended double-precision NaN. The
> +| `high' and `low' values hold the most- and least-significant bits,
> +| respectively.
> +*----------------------------------------------------------------------------*/
> +#if SNAN_BIT_IS_ONE
> +#define floatx80_default_nan_high 0x7FFF
> +#define floatx80_default_nan_low LIT64( 0xBFFFFFFFFFFFFFFF )
> +#else
> +#define floatx80_default_nan_high 0xFFFF
> +#define floatx80_default_nan_low LIT64( 0xC000000000000000 )
> +#endif
> +
> #endif
>
> #ifdef FLOAT128
> @@ -593,6 +650,18 @@ INLINE int float128_is_any_nan(float128 a)
> ((a.low != 0) || ((a.high & 0xffffffffffffLL) != 0));
> }
>
> +/*----------------------------------------------------------------------------
> +| The pattern for a default generated quadruple-precision NaN. The `high'
> and
> +| `low' values hold the most- and least-significant bits, respectively.
> +*----------------------------------------------------------------------------*/
> +#if SNAN_BIT_IS_ONE
> +#define float128_default_nan_high LIT64( 0x7FFF7FFFFFFFFFFF )
> +#define float128_default_nan_low LIT64( 0xFFFFFFFFFFFFFFFF )
> +#else
> +#define float128_default_nan_high LIT64( 0xFFFF800000000000 )
> +#define float128_default_nan_low LIT64( 0x0000000000000000 )
> +#endif
> +
> #endif
>
> #else /* CONFIG_SOFTFLOAT */
Reviewed-by: Aurelien Jarno <address@hidden>
--
Aurelien Jarno GPG: 1024D/F1BCDB73
address@hidden http://www.aurel32.net
- [Qemu-devel] [PATCH v4 0/4] ARM: fix Neon VRECPE and VRSQRTE instructions., Christophe Lyon, 2011/02/18
- [Qemu-devel] [PATCH 2/4] softfloat: add float32_set_sign(), float32_infinity, float64_half, float64_256 and float64_512., Christophe Lyon, 2011/02/18
- Re: [Qemu-devel] [PATCH 2/4] softfloat: add float32_set_sign(), float32_infinity, float64_half, float64_256 and float64_512., Aurelien Jarno, 2011/02/20
- Re: [Qemu-devel] [PATCH 2/4] softfloat: add float32_set_sign(), float32_infinity, float64_half, float64_256 and float64_512., Peter Maydell, 2011/02/20
- Re: [Qemu-devel] [PATCH 2/4] softfloat: add float32_set_sign(), float32_infinity, float64_half, float64_256 and float64_512., Aurelien Jarno, 2011/02/20
- Re: [Qemu-devel] [PATCH 2/4] softfloat: add float32_set_sign(), float32_infinity, float64_half, float64_256 and float64_512., Christophe Lyon, 2011/02/21
[Qemu-devel] [PATCH 3/4] target-arm: fix support for VRECPE., Christophe Lyon, 2011/02/18
[Qemu-devel] [PATCH 4/4] target-arm: fix support for VRSQRTE., Christophe Lyon, 2011/02/18
[Qemu-devel] [PATCH 1/4] softfloat: move all default NaN definitions to softfloat.h., Christophe Lyon, 2011/02/18
- Re: [Qemu-devel] [PATCH 1/4] softfloat: move all default NaN definitions to softfloat.h.,
Aurelien Jarno <=