[Qemu-devel] Re: RFC: New API for PPC for vcpu mmu access

[Alexander Graf]

On 14.02.2011, at 18:11, Scott Wood <address@hidden> wrote:

> On Sun, 13 Feb 2011 23:43:40 +0100
> Alexander Graf <address@hidden> wrote:
> 
>>> struct kvmppc_book3e_tlb_entry {
>>>    union {
>>>        __u64 mas8_1;
>>>        struct {
>>>            __u32 mas8;
>>>            __u32 mas1;
>>>        };
>>>    };
>>>    __u64 mas2;
>>>    union {
>>>        __u64 mas7_3    
>>>        struct {
>>>            __u32 mas7;
>>>            __u32 mas3;
>>>        };
>>>    };
>>> };
>> 
>> Looks good to me, except for the anonymous unions and structs of course. Avi 
>> dislikes those :). 
> 
> :-(
> 
>> Is there any obvious reason we need to have unions in the first place? The
>> compiler should be clever enough to pick the right size accessors when
>> writing/reading masked  __u64 entries, no?
> 
> Yes, the intent was just to make it easier to access individual mas
> registers, and reuse existing bit declarations that are defined relative
> to individual registers.
> 
> Why clutter up the source code when the compiler can deal with it?  Same
> applies to the anonymous unions/structs -- it's done that way to present
> the fields in the most straightforward manner (equivalent to how the SPRs
> themselves are named and aliased).
> 
> If it's a firm NACK on the existing structure, I think I'd rather just drop
> the paired versions altogether (but still order them this way so it can be
> changed back if there's any desire to in the future, without breaking
> compatibility).

There's no nack here :). The only thing that needs to change is the anonymous 
part, as that's a gnu extension. Just name the structs and unions and all is 
well.

The reason I was asking is that I assumed the code would end up being easier, 
not more complex without the u32s. In fact, it probably would. I'll leave the 
final decision if you want to access things by entry->u81.split.mas8 or 
entry->mas8_1 & MAS8_1_MAS8_MASK.

> 
>> The struct name should also have
>> a version indicator - it's the data descriptor only a single specific
>> mmu_type, right?
> 
> It handles both KVM_MMU_PPC_BOOK3E_NOHV and KVM_MMU_PPC_BOOK3E_HV.

Even fictional future changes to the tlb layout? Either way, we can name that 
differently when it comes.

> 
>>> For an MMU type of KVM_MMU_PPC_BOOK3E_NOHV, the mas8 in 
>>> kvmppc_book3e_tlb_entry is
>>> present but not supported.
>>> 
>>> struct kvmppc_book3e_tlb_params {
>>>    /*
>>>     * book3e defines 4 TLBs.  Individual implementations may have
>>>     * fewer.  TLBs that do not already exist on the target must be
>>>     * configured with a size of zero.  A tlb_ways value of zero means
>>>     * the array is fully associative.  Only TLBs that are already
>>>     * set-associative on the target may be configured with a different
>>>     * associativity.  A set-associative TLB may not exceed 255 ways.
>>>     *
>>>     * KVM will adjust TLBnCFG based on the sizes configured here,
>>>     * though arrays greater than 2048 entries will have TLBnCFG[NENTRY]
>>>     * set to zero.
>>>     *
>>>     * The size of any TLB that is set-associative must be a multiple of
>>>     * the number of ways, and the number of sets must be a power of two.
>>>     *
>>>     * The page sizes supported by a TLB shall be determined by reading
>>>     * the TLB configuration registers.  This is not adjustable by userspace.
>>>     * [Note: need sregs]
>>>     */
>>>    __u32 tlb_sizes[4];
>>>    __u8 tlb_ways[4];
>>>    __u32 reserved[11];
>>> };
>>> 
>>> KVM_CONFIG_TLB
>>> --------------
>>> 
>>> Capability: KVM_CAP_SW_TLB
>>> Type: vcpu ioctl
>>> Parameters: struct kvm_config_tlb (in)
>>> Returns: 0 on success
>>>        -1 on error
>>> 
>>> struct kvm_config_tlb {
>>>    __u64 params;
>>>    __u64 array;
>>>    __u32 mmu_type;
>>>    __u32 array_len;
>> 
>> Some reserved bits please. IIRC Avi also really likes it when in addition to 
>> reserved fields there's also a "features" int that indicates which reserved 
>> fields are actually usable. Shouldn't hurt here either, right?
> 
> params itself is a versioned struct, with reserved bits.  Do we really need
> it here as well?

Right. Probably not :).

> 
>>> - The hash for determining set number is:
>>>    (MAS2[EPN] / page_size) & (num_sets - 1)
>>>  where "page_size" is the smallest page size supported by the TLB, and
>>>  "num_sets" is the tlb_sizes[] value divided by the tlb_ways[] value.
>>>  If a book3e chip is made for which a different hash is needed, a new
>>>  MMU type must be used, to ensure that userspace and KVM agree on layout.
>> 
>> Please state the size explicitly then. It's 1k, right?
> 
> It's 4K on Freescale chips.  We should probably implement sregs first, in
> which case qemu can read the MMU config registers to find out the minimum
> supported page size.
> 
> If we specify 4K here, we should probably just go ahead and stick FSL in
> the MMU type name.  Specifying the hash itself already makes me nervous
> about claiming the more generic name.

Yup, sounds good :).


Alex

>