[Top][All Lists]
[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]
Re: [Qemu-devel] [PATCH 2/4] target-arm: Refactor translation of excepti
From: |
Aurelien Jarno |
Subject: |
Re: [Qemu-devel] [PATCH 2/4] target-arm: Refactor translation of exception generating instructions |
Date: |
Wed, 12 Jan 2011 00:07:30 +0100 |
User-agent: |
Mutt/1.5.20 (2009-06-14) |
On Mon, Jan 10, 2011 at 11:11:50PM +0000, Peter Maydell wrote:
> Create a new function which does the common sequence of gen_set_condexec,
> gen_set_pc_im, gen_exception, set is_jmp to DISAS_JUMP.
>
> Signed-off-by: Peter Maydell <address@hidden>
> ---
> target-arm/translate.c | 43 +++++++++++++++----------------------------
> 1 files changed, 15 insertions(+), 28 deletions(-)
Reviewed-by: Aurelien Jarno <address@hidden>
> diff --git a/target-arm/translate.c b/target-arm/translate.c
> index 4abece1..0e8f7b3 100644
> --- a/target-arm/translate.c
> +++ b/target-arm/translate.c
> @@ -3488,6 +3488,14 @@ gen_set_condexec (DisasContext *s)
> }
> }
>
> +static void gen_exception_insn(DisasContext *s, int offset, int excp)
> +{
> + gen_set_condexec(s);
> + gen_set_pc_im(s->pc - offset);
> + gen_exception(excp);
> + s->is_jmp = DISAS_JUMP;
> +}
> +
> static void gen_nop_hint(DisasContext *s, int val)
> {
> switch (val) {
> @@ -5958,10 +5966,7 @@ static void gen_store_exclusive(DisasContext *s, int
> rd, int rt, int rt2,
> tcg_gen_mov_i32(cpu_exclusive_test, addr);
> tcg_gen_movi_i32(cpu_exclusive_info,
> size | (rd << 4) | (rt << 8) | (rt2 << 12));
> - gen_set_condexec(s);
> - gen_set_pc_im(s->pc - 4);
> - gen_exception(EXCP_STREX);
> - s->is_jmp = DISAS_JUMP;
> + gen_exception_insn(s, 4, EXCP_STREX);
> }
> #else
> static void gen_store_exclusive(DisasContext *s, int rd, int rt, int rt2,
> @@ -6366,10 +6371,7 @@ static void disas_arm_insn(CPUState * env,
> DisasContext *s)
> goto illegal_op;
> }
> /* bkpt */
> - gen_set_condexec(s);
> - gen_set_pc_im(s->pc - 4);
> - gen_exception(EXCP_BKPT);
> - s->is_jmp = DISAS_JUMP;
> + gen_exception_insn(s, 4, EXCP_BKPT);
> break;
> case 0x8: /* signed multiply */
> case 0xa:
> @@ -7268,10 +7270,7 @@ static void disas_arm_insn(CPUState * env,
> DisasContext *s)
> break;
> default:
> illegal_op:
> - gen_set_condexec(s);
> - gen_set_pc_im(s->pc - 4);
> - gen_exception(EXCP_UDEF);
> - s->is_jmp = DISAS_JUMP;
> + gen_exception_insn(s, 4, EXCP_UDEF);
> break;
> }
> }
> @@ -8925,10 +8924,7 @@ static void disas_thumb_insn(CPUState *env,
> DisasContext *s)
> break;
>
> case 0xe: /* bkpt */
> - gen_set_condexec(s);
> - gen_set_pc_im(s->pc - 2);
> - gen_exception(EXCP_BKPT);
> - s->is_jmp = DISAS_JUMP;
> + gen_exception_insn(s, 2, EXCP_BKPT);
> break;
>
> case 0xa: /* rev */
> @@ -9050,17 +9046,11 @@ static void disas_thumb_insn(CPUState *env,
> DisasContext *s)
> }
> return;
> undef32:
> - gen_set_condexec(s);
> - gen_set_pc_im(s->pc - 4);
> - gen_exception(EXCP_UDEF);
> - s->is_jmp = DISAS_JUMP;
> + gen_exception_insn(s, 4, EXCP_UDEF);
> return;
> illegal_op:
> undef:
> - gen_set_condexec(s);
> - gen_set_pc_im(s->pc - 2);
> - gen_exception(EXCP_UDEF);
> - s->is_jmp = DISAS_JUMP;
> + gen_exception_insn(s, 2, EXCP_UDEF);
> }
>
> /* generate intermediate code in gen_opc_buf and gen_opparam_buf for
> @@ -9149,10 +9139,7 @@ static inline void
> gen_intermediate_code_internal(CPUState *env,
> if (unlikely(!QTAILQ_EMPTY(&env->breakpoints))) {
> QTAILQ_FOREACH(bp, &env->breakpoints, entry) {
> if (bp->pc == dc->pc) {
> - gen_set_condexec(dc);
> - gen_set_pc_im(dc->pc);
> - gen_exception(EXCP_DEBUG);
> - dc->is_jmp = DISAS_JUMP;
> + gen_exception_insn(dc, 0, EXCP_DEBUG);
> /* Advance PC so that clearing the breakpoint will
> invalidate this TB. */
> dc->pc += 2;
> --
> 1.7.1
>
>
>
--
Aurelien Jarno GPG: 1024D/F1BCDB73
address@hidden http://www.aurel32.net
- [Qemu-devel] [PATCH 0/4] target-arm: get IT bits right at exceptions, Peter Maydell, 2011/01/10
- [Qemu-devel] [PATCH 4/4] target-arm: Restore IT bits when resuming after an exception, Peter Maydell, 2011/01/10
- [Qemu-devel] [PATCH 1/4] target-arm: Remove redundant setting of IT bits before Thumb SWI, Peter Maydell, 2011/01/10
- [Qemu-devel] [PATCH 3/4] linux-user: ARM: clear the IT bits when invoking a signal handler, Peter Maydell, 2011/01/10
- [Qemu-devel] [PATCH 2/4] target-arm: Refactor translation of exception generating instructions, Peter Maydell, 2011/01/10
- Re: [Qemu-devel] [PATCH 2/4] target-arm: Refactor translation of exception generating instructions,
Aurelien Jarno <=
- Re: [Qemu-devel] [PATCH 0/4] target-arm: get IT bits right at exceptions, Aurelien Jarno, 2011/01/14