[Qemu-devel] [PATCH 17/34] ac97: convert to pci_bar_map

[Blue Swirl]

Use pci_bar_map() and post_map_func instead of a mapping function.

Signed-off-by: Blue Swirl <address@hidden>
---
 hw/ac97.c |   59 ++++++++++++++++++++++++++++++++++++++---------------------
 1 files changed, 38 insertions(+), 21 deletions(-)

diff --git a/hw/ac97.c b/hw/ac97.c
index ad4aef4..2e5f02c 100644
--- a/hw/ac97.c
+++ b/hw/ac97.c
@@ -1234,29 +1234,39 @@ static const VMStateDescription vmstate_ac97 = {
     }
 };

-static void ac97_map (PCIDevice *pci_dev, int region_num,
-                      pcibus_t addr, pcibus_t size, int type)
+static IOPortWriteFunc * const nam_writes[] = {
+    nam_writeb,
+    nam_writew,
+    nam_writel,
+};
+
+static IOPortReadFunc * const nam_reads[] = {
+    nam_readb,
+    nam_readw,
+    nam_readl,
+};
+
+static IOPortWriteFunc * const nabm_writes[] = {
+    nabm_writeb,
+    nabm_writew,
+    nabm_writel,
+};
+
+static IOPortReadFunc * const nabm_reads[] = {
+    nabm_readb,
+    nabm_readw,
+    nabm_readl,
+};
+
+static void ac97_post_map (PCIDevice *pci_dev, int region_num,
+                           pcibus_t addr, pcibus_t size, int type)
 {
     AC97LinkState *s = DO_UPCAST (AC97LinkState, dev, pci_dev);
-    PCIDevice *d = &s->dev;

     if (!region_num) {
         s->base[0] = addr;
-        register_ioport_read (addr, 256 * 1, 1, nam_readb, d);
-        register_ioport_read (addr, 256 * 2, 2, nam_readw, d);
-        register_ioport_read (addr, 256 * 4, 4, nam_readl, d);
-        register_ioport_write (addr, 256 * 1, 1, nam_writeb, d);
-        register_ioport_write (addr, 256 * 2, 2, nam_writew, d);
-        register_ioport_write (addr, 256 * 4, 4, nam_writel, d);
-    }
-    else {
+    } else {
         s->base[1] = addr;
-        register_ioport_read (addr, 64 * 1, 1, nabm_readb, d);
-        register_ioport_read (addr, 64 * 2, 2, nabm_readw, d);
-        register_ioport_read (addr, 64 * 4, 4, nabm_readl, d);
-        register_ioport_write (addr, 64 * 1, 1, nabm_writeb, d);
-        register_ioport_write (addr, 64 * 2, 2, nabm_writew, d);
-        register_ioport_write (addr, 64 * 4, 4, nabm_writel, d);
     }
 }

@@ -1280,6 +1290,7 @@ static int ac97_initfn (PCIDevice *dev)
 {
     AC97LinkState *s = DO_UPCAST (AC97LinkState, dev, dev);
     uint8_t *c = s->dev.config;
+    int io_index;

     pci_config_set_vendor_id (c, PCI_VENDOR_ID_INTEL); /* ro */
     pci_config_set_device_id (c, PCI_DEVICE_ID_INTEL_82801AA_5); /* ro */
@@ -1320,10 +1331,16 @@ static int ac97_initfn (PCIDevice *dev)
     /* TODO: RST# value should be 0. */
     c[PCI_INTERRUPT_PIN] = 0x01;      /* intr_pn interrupt pin ro */

-    pci_register_bar (&s->dev, 0, 256 * 4, PCI_BASE_ADDRESS_SPACE_IO,
-                      ac97_map, NULL);
-    pci_register_bar (&s->dev, 1, 64 * 4, PCI_BASE_ADDRESS_SPACE_IO, ac97_map,
-                      NULL);
+    pci_register_bar (&s->dev, 0, 256 * 4, PCI_BASE_ADDRESS_SPACE_IO, NULL,
+                      ac97_post_map);
+    io_index = cpu_register_io (nam_reads, nam_writes, 256 * 4, s);
+    pci_bar_map (&s->dev, 0, 0, 0, 256 * 4, io_index);
+
+    pci_register_bar (&s->dev, 1, 64 * 4, PCI_BASE_ADDRESS_SPACE_IO, NULL,
+                      ac97_post_map);
+    io_index = cpu_register_io (nabm_reads, nabm_writes, 64 * 4, s);
+    pci_bar_map (&s->dev, 1, 0, 0, 64 * 4, io_index);
+
     qemu_register_reset (ac97_on_reset, s);
     AUD_register_card ("ac97", &s->card);
     ac97_on_reset (s);
-- 
1.6.2.4