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[Qemu-devel] Re: [PATCH] [sparc32] mask all interrupts when MASTER_DISAB
From: |
Blue Swirl |
Subject: |
[Qemu-devel] Re: [PATCH] [sparc32] mask all interrupts when MASTER_DISABLE is set |
Date: |
Sun, 27 Jun 2010 20:22:50 +0000 |
Thanks, applied.
On Mon, Jun 21, 2010 at 6:23 PM, Artyom Tarasenko
<address@hidden> wrote:
> The MASTER_DISABLE bit (aka mask-all) masks all the interrupts.
>
> According to Sun-4M System Architecture
> "The level–15 interrupt sources [...] are maskable with the Interrupt Target
> Mask Register. While these interrupts are considered ’non–maskable’ within
> the SPARC IU, a mask capability is provided to allow the boot firmware
> to establish a basic environment before receiving any level–15 interrupts,
> which are non–maskable within SPARC. A mask–all bit is provided to allow
> disabling of all external interrupts during change of the CIT."
>
> Signed-off-by: Artyom Tarasenko <address@hidden>
> ---
> hw/slavio_intctl.c | 9 ++++++---
> 1 files changed, 6 insertions(+), 3 deletions(-)
>
> diff --git a/hw/slavio_intctl.c b/hw/slavio_intctl.c
> index b76d3ac..8a38f67 100644
> --- a/hw/slavio_intctl.c
> +++ b/hw/slavio_intctl.c
> @@ -289,9 +289,12 @@ static void slavio_check_interrupts(SLAVIO_INTCTLState
> *s, int set_irqs)
> }
> }
>
> - /* Level 15 and CPU timer interrupts are not maskable */
> - pil_pending |= s->slaves[i].intreg_pending &
> - (CPU_IRQ_INT15_IN | CPU_IRQ_TIMER_IN);
> + /* Level 15 and CPU timer interrupts are only masked when
> + the MASTER_DISABLE bit is set */
> + if (!(s->intregm_disabled & MASTER_DISABLE)) {
> + pil_pending |= s->slaves[i].intreg_pending &
> + (CPU_IRQ_INT15_IN | CPU_IRQ_TIMER_IN);
> + }
>
> /* Add soft interrupts */
> pil_pending |= (s->slaves[i].intreg_pending & CPU_SOFTIRQ_MASK) >> 16;
> --
> 1.6.2.5
>
>