Re: [Qemu-devel] [PATCH 15/35] tcg-s390: Query instruction extensions that are installed.

[Aurelien Jarno]

On Fri, Jun 04, 2010 at 12:14:23PM -0700, Richard Henderson wrote:
> Verify that we have all the instruction extensions that we generate.
> Future patches can tailor code generation to the set of instructions
> that are present.
> 
> Signed-off-by: Richard Henderson <address@hidden>
> ---
>  tcg/s390/tcg-target.c |  113 
> +++++++++++++++++++++++++++++++++++++++++++++++++
>  1 files changed, 113 insertions(+), 0 deletions(-)
> 
> diff --git a/tcg/s390/tcg-target.c b/tcg/s390/tcg-target.c
> index 3944cb1..d99bb5c 100644
> --- a/tcg/s390/tcg-target.c
> +++ b/tcg/s390/tcg-target.c
> @@ -229,6 +229,17 @@ static void *qemu_st_helpers[4] = {
>  
>  static uint8_t *tb_ret_addr;
>  
> +/* A list of relevant facilities used by this translator.  Some of these
> +   are required for proper operation, and these are checked at startup.  */
> +
> +#define FACILITY_ZARCH               (1ULL << (63 - 1))
> +#define FACILITY_ZARCH_ACTIVE        (1ULL << (63 - 2))
> +#define FACILITY_LONG_DISP   (1ULL << (63 - 18))
> +#define FACILITY_EXT_IMM     (1ULL << (63 - 21))
> +#define FACILITY_GEN_INST_EXT        (1ULL << (63 - 34))
> +
> +static uint64_t facilities;
> +
>  static void patch_reloc(uint8_t *code_ptr, int type,
>                  tcg_target_long value, tcg_target_long addend)
>  {
> @@ -1177,6 +1188,106 @@ static const TCGTargetOpDef s390_op_defs[] = {
>      { -1 },
>  };
>  
> +/* ??? Linux kernels provide an AUXV entry AT_HWCAP that provides most of
> +   this information.  However, getting at that entry is not easy this far
> +   away from main.  Our options are: start searching from environ, but
> +   that fails as soon as someone does a setenv in between.  Read the data
> +   from /proc/self/auxv.  Or do the probing ourselves.  The only thing
> +   extra that AT_HWCAP gives us is HWCAP_S390_HIGH_GPRS, which indicates
> +   that the kernel saves all 64-bits of the registers around traps while
> +   in 31-bit mode.  But this is true of all "recent" kernels (ought to dig
> +   back and see from when this might not be true).  */
> +
> +#include <signal.h>
> +
> +static volatile sig_atomic_t got_sigill;
> +
> +static void sigill_handler(int sig)
> +{
> +    got_sigill = 1;
> +}
> +
> +static void query_facilities(void)
> +{
> +    struct sigaction sa_old, sa_new;
> +    register int r0 __asm__("0");
> +    register void *r1 __asm__("1");
> +    int fail;
> +
> +    memset(&sa_new, 0, sizeof(sa_new));
> +    sa_new.sa_handler = sigill_handler;
> +    sigaction(SIGILL, &sa_new, &sa_old);
> +
> +    /* First, try STORE FACILITY LIST EXTENDED.  If this is present, then
> +       we need not do any more probing.  Unfortunately, this itself is an
> +       extension and the original STORE FACILITY LIST instruction is
> +       kernel-only, storing its results at absolute address 200.  */
> +    /* stfle 0(%r1) */
> +    r1 = &facilities;
> +    asm volatile(".word 0xb2b0,0x1000"
> +                 : "=r"(r0) : "0"(0), "r"(r1) : "memory", "cc");

Wouldn't it be possible to use the instruction directly instead of
dumping the opcode values? Same below

> +
> +    if (got_sigill) {
> +        /* STORE FACILITY EXTENDED is not available.  Probe for one of each
> +           kind of instruction that we're interested in.  */
> +        /* ??? Possibly some of these are in practice never present unless
> +           the store-facility-extended facility is also present.  But since
> +           that isn't documented it's just better to probe for each.  */
> +
> +        /* Test for z/Architecture.  Required even in 31-bit mode.  */
> +        got_sigill = 0;
> +        /* agr %r0,%r0 */
> +        asm volatile(".word 0xb908,0x0000" : "=r"(r0) : : "cc");
> +        if (!got_sigill) {
> +            facilities |= FACILITY_ZARCH | FACILITY_ZARCH_ACTIVE;
> +        }
> +
> +        /* Test for long displacement.  */
> +        got_sigill = 0;
> +        /* ly %r0,0(%r1) */
> +        r1 = &facilities;
> +        asm volatile(".word 0xe300,0x1000,0x0058"
> +                     : "=r"(r0) : "r"(r1) : "cc");
> +        if (!got_sigill) {
> +            facilities |= FACILITY_LONG_DISP;
> +        }
> +
> +        /* Test for extended immediates.  */
> +        got_sigill = 0;
> +        /* afi %r0,0 */
> +        asm volatile(".word 0xc209,0x0000,0x0000" : : : "cc");
> +        if (!got_sigill) {
> +            facilities |= FACILITY_EXT_IMM;
> +        }
> +
> +        /* Test for general-instructions-extension.  */
> +        got_sigill = 0;
> +        /* msfi %r0,1 */
> +        asm volatile(".word 0xc201,0x0000,0x0001");
> +        if (!got_sigill) {
> +            facilities |= FACILITY_GEN_INST_EXT;
> +        }
> +    }
> +
> +    sigaction(SIGILL, &sa_old, NULL);
> +
> +    /* The translator currently uses these extensions unconditionally.
> +       Pruning this back to the base ESA/390 architecture doesn't seem
> +       worthwhile, since even the KVM target requires z/Arch.  */
> +    fail = 0;
> +    if ((facilities & FACILITY_ZARCH_ACTIVE) == 0) {
> +        fprintf(stderr, "TCG: z/Arch facility is required\n");
> +        fail = 1;
> +    }
> +    if ((facilities & FACILITY_LONG_DISP) == 0) {
> +        fprintf(stderr, "TCG: long-displacement facility is required\n");
> +        fail = 1;
> +    }
> +    if (fail) {
> +        exit(-1);
> +    }
> +}
> +
>  void tcg_target_init(TCGContext *s)
>  {
>  #if !defined(CONFIG_USER_ONLY)
> @@ -1186,6 +1297,8 @@ void tcg_target_init(TCGContext *s)
>      }
>  #endif
>  
> +    query_facilities();
> +
>      tcg_regset_set32(tcg_target_available_regs[TCG_TYPE_I32], 0, 0xffff);
>      tcg_regset_set32(tcg_target_available_regs[TCG_TYPE_I64], 0, 0xffff);
>  
> -- 
> 1.7.0.1
> 
> 
> 

-- 
Aurelien Jarno                          GPG: 1024D/F1BCDB73
address@hidden                 http://www.aurel32.net