[Qemu-devel] Re: [PATCH] sparc32 esp fix spurious interrupts in chip reset

[Blue Swirl]

On Sun, May 30, 2010 at 10:35 PM, Artyom Tarasenko
<address@hidden> wrote:
> lower interrupt during chip reset. Otherwise the ESP_RSTAT register
> may get out of sync with the IRQ line status. This effect became
> visible after commit 65899fe3

Hard reset handlers should not touch qemu_irqs, because on cold start,
the receiving end may be unprepared to handle the signal. See
0d0a7e69e853639b123798877e019c3c7ee6634a,
bc26e55a6615dc594be425d293db40d5cdcdb84b and
42f1ced228c9b616cfa2b69846025271618e4ef5.

For ESP there are two other sources of reset: signal from DMA and chip
reset command. On those cases, lowering IRQ makes sense.

So the correct fix is to refactor the reset handling a bit. Does this
patch also fix your test case?

0001-esp-lower-IRQ-on-soft-reset.patch
Description: Source code patch