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[Qemu-devel] [PATCH 01/10] target-alpha: Implement cpys{, n, e} inline.
From: |
Richard Henderson |
Subject: |
[Qemu-devel] [PATCH 01/10] target-alpha: Implement cpys{, n, e} inline. |
Date: |
Mon, 12 Apr 2010 16:12:20 -0700 |
Signed-off-by: Richard Henderson <address@hidden>
---
target-alpha/helper.h | 4 --
target-alpha/op_helper.c | 18 ----------
target-alpha/translate.c | 79 +++++++++++++++++++++++++++++++++++++++++++--
3 files changed, 75 insertions(+), 26 deletions(-)
diff --git a/target-alpha/helper.h b/target-alpha/helper.h
index 6072a26..73413f2 100644
--- a/target-alpha/helper.h
+++ b/target-alpha/helper.h
@@ -77,10 +77,6 @@ DEF_HELPER_FLAGS_2(cmpgeq, TCG_CALL_CONST | TCG_CALL_PURE,
i64, i64, i64)
DEF_HELPER_FLAGS_2(cmpgle, TCG_CALL_CONST | TCG_CALL_PURE, i64, i64, i64)
DEF_HELPER_FLAGS_2(cmpglt, TCG_CALL_CONST | TCG_CALL_PURE, i64, i64, i64)
-DEF_HELPER_FLAGS_2(cpys, TCG_CALL_CONST | TCG_CALL_PURE, i64, i64, i64)
-DEF_HELPER_FLAGS_2(cpysn, TCG_CALL_CONST | TCG_CALL_PURE, i64, i64, i64)
-DEF_HELPER_FLAGS_2(cpyse, TCG_CALL_CONST | TCG_CALL_PURE, i64, i64, i64)
-
DEF_HELPER_FLAGS_1(cvtts, TCG_CALL_CONST, i64, i64)
DEF_HELPER_FLAGS_1(cvtst, TCG_CALL_CONST, i64, i64)
DEF_HELPER_FLAGS_1(cvtqs, TCG_CALL_CONST, i64, i64)
diff --git a/target-alpha/op_helper.c b/target-alpha/op_helper.c
index dd1af84..ded71f6 100644
--- a/target-alpha/op_helper.c
+++ b/target-alpha/op_helper.c
@@ -921,24 +921,6 @@ uint64_t helper_sqrtt (uint64_t a)
return float64_to_t(fr);
}
-
-/* Sign copy */
-uint64_t helper_cpys(uint64_t a, uint64_t b)
-{
- return (a & 0x8000000000000000ULL) | (b & ~0x8000000000000000ULL);
-}
-
-uint64_t helper_cpysn(uint64_t a, uint64_t b)
-{
- return ((~a) & 0x8000000000000000ULL) | (b & ~0x8000000000000000ULL);
-}
-
-uint64_t helper_cpyse(uint64_t a, uint64_t b)
-{
- return (a & 0xFFF0000000000000ULL) | (b & ~0xFFF0000000000000ULL);
-}
-
-
/* Comparisons */
uint64_t helper_cmptun (uint64_t a, uint64_t b)
{
diff --git a/target-alpha/translate.c b/target-alpha/translate.c
index d903800..817194e 100644
--- a/target-alpha/translate.c
+++ b/target-alpha/translate.c
@@ -774,6 +774,81 @@ static inline void glue(gen_f, name)(DisasContext *ctx,
\
IEEE_INTCVT(cvtqs)
IEEE_INTCVT(cvtqt)
+static void gen_cpys_internal(int ra, int rb, int rc, int inv_a, uint64_t mask)
+{
+ TCGv va, vb, vmask;
+ int za = 0, zb = 0;
+
+ if (unlikely(rc == 31)) {
+ return;
+ }
+
+ vmask = tcg_const_i64(mask);
+
+ TCGV_UNUSED_I64(va);
+ if (ra == 31) {
+ if (inv_a) {
+ va = vmask;
+ } else {
+ za = 1;
+ }
+ } else {
+ va = tcg_temp_new_i64();
+ tcg_gen_mov_i64(va, cpu_fir[ra]);
+ if (inv_a) {
+ tcg_gen_andc_i64(va, vmask, va);
+ } else {
+ tcg_gen_and_i64(va, va, vmask);
+ }
+ }
+
+ TCGV_UNUSED_I64(vb);
+ if (rb == 31) {
+ zb = 1;
+ } else {
+ vb = tcg_temp_new_i64();
+ tcg_gen_andc_i64(vb, cpu_fir[rb], vmask);
+ }
+
+ switch (za << 1 | zb) {
+ case 0 | 0:
+ tcg_gen_or_i64(cpu_fir[rc], va, vb);
+ break;
+ case 0 | 1:
+ tcg_gen_mov_i64(cpu_fir[rc], va);
+ break;
+ case 2 | 0:
+ tcg_gen_mov_i64(cpu_fir[rc], vb);
+ break;
+ case 2 | 1:
+ tcg_gen_movi_i64(cpu_fir[rc], 0);
+ break;
+ }
+
+ tcg_temp_free(vmask);
+ if (ra != 31) {
+ tcg_temp_free(va);
+ }
+ if (rb != 31) {
+ tcg_temp_free(vb);
+ }
+}
+
+static inline void gen_fcpys(int ra, int rb, int rc)
+{
+ gen_cpys_internal(ra, rb, rc, 0, 0x8000000000000000ULL);
+}
+
+static inline void gen_fcpysn(int ra, int rb, int rc)
+{
+ gen_cpys_internal(ra, rb, rc, 1, 0x8000000000000000ULL);
+}
+
+static inline void gen_fcpyse(int ra, int rb, int rc)
+{
+ gen_cpys_internal(ra, rb, rc, 0, 0xFFF0000000000000ULL);
+}
+
#define FARITH3(name) \
static inline void glue(gen_f, name)(int ra, int rb, int rc) \
{ \
@@ -802,10 +877,6 @@ static inline void glue(gen_f, name)(int ra, int rb, int
rc) \
tcg_temp_free(vb); \
} \
}
-/* ??? Ought to expand these inline; simple masking operations. */
-FARITH3(cpys)
-FARITH3(cpysn)
-FARITH3(cpyse)
/* ??? VAX instruction qualifiers ignored. */
FARITH3(addf)
--
1.6.2.5
- [Qemu-devel] [PATCH 08/13] target-alpha: Emit goto_tb opcodes., (continued)
- [Qemu-devel] [PATCH 08/13] target-alpha: Emit goto_tb opcodes., Richard Henderson, 2010/04/07
- [Qemu-devel] [PATCH 13/13] target-alpha: Implement RPCC., Richard Henderson, 2010/04/07
- [Qemu-devel] [PATCH 12/13] target-alpha: Fix load-locked/store-conditional., Richard Henderson, 2010/04/07
- [Qemu-devel] [PATCH 00/10] target-alpha improvments, version 5, Richard Henderson, 2010/04/12
- [Qemu-devel] [PATCH 03/10] target-alpha: Implement cvtlq inline., Richard Henderson, 2010/04/12
- [Qemu-devel] [PATCH 05/10] target-alpha: Update commentary for opcode 0x1A., Richard Henderson, 2010/04/12
- [Qemu-devel] [PATCH 04/10] target-alpha: Emit goto_tb opcodes., Richard Henderson, 2010/04/12
- [Qemu-devel] [PATCH 08/10] target-alpha: Fix load-locked/store-conditional., Richard Henderson, 2010/04/12
- [Qemu-devel] [PATCH 07/10] target-alpha: Indicate NORETURN status when raising exception., Richard Henderson, 2010/04/12
- [Qemu-devel] [PATCH 01/10] target-alpha: Implement cpys{, n, e} inline.,
Richard Henderson <=
- [Qemu-devel] [PATCH 06/10] target-alpha: Enable NPTL., Richard Henderson, 2010/04/12
- [Qemu-devel] [PATCH 10/10] Implement cpu_get_real_ticks for Alpha., Richard Henderson, 2010/04/12
- [Qemu-devel] [PATCH 02/10] target-alpha: Implement rs/rc properly., Richard Henderson, 2010/04/12
- [Qemu-devel] [PATCH 09/10] target-alpha: Implement RPCC., Richard Henderson, 2010/04/12