Re: [Qemu-devel] [PATCH] target-ppc: fix SPE evcmp* instructions

[Aurelien Jarno]

On Tue, Feb 23, 2010 at 11:55:14AM -0800, Nathan Froyd wrote:
> The CRF_{CH,CL,CH_OR_CL,CH_AND_CL} constants were all off by one bit
> position.  Because of this, the SPE evcmp* family of instructions would
> store values in the result condition register that were also off by one
> bit position.
> 
> Fixed by using the CRF_{LT,GT,EQ,SO} constants for the shift amounts.
> 
> Signed-off-by: Nathan Froyd <address@hidden>

Thanks, applied.

> ---
>  target-ppc/cpu.h |    8 ++++----
>  1 files changed, 4 insertions(+), 4 deletions(-)
> 
> diff --git a/target-ppc/cpu.h b/target-ppc/cpu.h
> index d15bba1..63aeb86 100644
> --- a/target-ppc/cpu.h
> +++ b/target-ppc/cpu.h
> @@ -834,10 +834,10 @@ static inline void cpu_clone_regs(CPUState *env, 
> target_ulong newsp)
>  #define CRF_GT        2
>  #define CRF_EQ        1
>  #define CRF_SO        0
> -#define CRF_CH        (1 << 4)
> -#define CRF_CL        (1 << 3)
> -#define CRF_CH_OR_CL  (1 << 2)
> -#define CRF_CH_AND_CL (1 << 1)
> +#define CRF_CH        (1 << CRF_LT)
> +#define CRF_CL        (1 << CRF_GT)
> +#define CRF_CH_OR_CL  (1 << CRF_EQ)
> +#define CRF_CH_AND_CL (1 << CRF_SO)
>  
>  /* XER definitions */
>  #define XER_SO  31
> -- 
> 1.6.3.2
> 
> 
> 
> 

-- 
Aurelien Jarno                          GPG: 1024D/F1BCDB73
address@hidden                 http://www.aurel32.net