[Qemu-devel] [PATCH] target-mips: fix CpU exception for coprocessor 0

[Nathan Froyd]

When we signal a CpU exception for coprocessor 0, we should indicate
that it's for coprocessor 0 instead of coprocessor 1.

Signed-off-by: Nathan Froyd <address@hidden>
---
 target-mips/translate.c |    2 +-
 1 files changed, 1 insertions(+), 1 deletions(-)

diff --git a/target-mips/translate.c b/target-mips/translate.c
index dfea6f6..f3522f5 100644
--- a/target-mips/translate.c
+++ b/target-mips/translate.c
@@ -830,7 +830,7 @@ static inline void gen_op_addr_add (DisasContext *ctx, TCGv 
ret, TCGv arg0, TCGv
 static inline void check_cp0_enabled(DisasContext *ctx)
 {
     if (unlikely(!(ctx->hflags & MIPS_HFLAG_CP0)))
-        generate_exception_err(ctx, EXCP_CpU, 1);
+        generate_exception_err(ctx, EXCP_CpU, 0);
 }
 
 static inline void check_cp1_enabled(DisasContext *ctx)
-- 
1.6.3.2