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[Qemu-devel] [PATCH 2/8] target-sh4: MMU: fix mem_idx computation
From: |
Aurelien Jarno |
Subject: |
[Qemu-devel] [PATCH 2/8] target-sh4: MMU: fix mem_idx computation |
Date: |
Sat, 6 Feb 2010 17:43:37 +0100 |
The mem_idx is wrongly computed. As written in target-sh4/cpu.h, mode 0
corresponds to kernel mode (SR_MD = 1), while mode 1 corresponds to user
mode (SR_MD = 0).
Signed-off-by: Aurelien Jarno <address@hidden>
---
target-sh4/translate.c | 2 +-
1 files changed, 1 insertions(+), 1 deletions(-)
diff --git a/target-sh4/translate.c b/target-sh4/translate.c
index 8f0a986..bff3188 100644
--- a/target-sh4/translate.c
+++ b/target-sh4/translate.c
@@ -1905,7 +1905,7 @@ gen_intermediate_code_internal(CPUState * env,
TranslationBlock * tb,
ctx.bstate = BS_NONE;
ctx.sr = env->sr;
ctx.fpscr = env->fpscr;
- ctx.memidx = (env->sr & SR_MD) ? 1 : 0;
+ ctx.memidx = (env->sr & SR_MD) == 0 ? 1 : 0;
/* We don't know if the delayed pc came from a dynamic or static branch,
so assume it is a dynamic branch. */
ctx.delayed_pc = -1; /* use delayed pc from env pointer */
--
1.6.6.1
- [Qemu-devel] [PATCH 0/8] SH4 MMU fixes and optimisation, Aurelien Jarno, 2010/02/06
- [Qemu-devel] [PATCH 7/8] target-sh4: MMU: remove dead code, Aurelien Jarno, 2010/02/06
- [Qemu-devel] [PATCH 2/8] target-sh4: MMU: fix mem_idx computation,
Aurelien Jarno <=
- [Qemu-devel] [PATCH 6/8] target-sh4: MMU: reduce the size of a TLB entry, Aurelien Jarno, 2010/02/06
- [Qemu-devel] [PATCH 8/8] target-sh4: MMU: fix store queue addresses, Aurelien Jarno, 2010/02/06
- [Qemu-devel] [PATCH 3/8] target-sh4: MMU: simplify call to tlb_set_page(), Aurelien Jarno, 2010/02/06
- [Qemu-devel] [PATCH 1/8] sh7750: handle MMUCR TI bit, Aurelien Jarno, 2010/02/06
- [Qemu-devel] [PATCH 5/8] target-sh4: MMU: optimize UTLB accesses, Aurelien Jarno, 2010/02/06
- [Qemu-devel] [PATCH 4/8] target-sh4: MMU: fix ITLB priviledge check, Aurelien Jarno, 2010/02/06