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Re: [Qemu-devel] [PATCH 1/9] sparc64: trace pstate and global register
From: |
Blue Swirl |
Subject: |
Re: [Qemu-devel] [PATCH 1/9] sparc64: trace pstate and global register set changes |
Date: |
Wed, 6 Jan 2010 15:24:25 +0000 |
On Tue, Jan 5, 2010 at 11:19 PM, Igor V. Kovalenko
<address@hidden> wrote:
> From: Igor V. Kovalenko <address@hidden>
>
> Signed-off-by: Igor V. Kovalenko <address@hidden>
> ---
> target-sparc/op_helper.c | 20 ++++++++++++++++++++
> 1 files changed, 20 insertions(+), 0 deletions(-)
>
> diff --git a/target-sparc/op_helper.c b/target-sparc/op_helper.c
> index dab2c25..26092e5 100644
> --- a/target-sparc/op_helper.c
> +++ b/target-sparc/op_helper.c
> @@ -11,6 +11,7 @@
> //#define DEBUG_UNASSIGNED
> //#define DEBUG_ASI
> //#define DEBUG_PCALL
> +//#define DEBUG_PSTATE
>
> #ifdef DEBUG_MMU
> #define DPRINTF_MMU(fmt, ...) \
> @@ -31,6 +32,13 @@
> do { printf("ASI: " fmt , ## __VA_ARGS__); } while (0)
> #endif
>
> +#ifdef DEBUG_PSTATE
> +#define DPRINTF_PSTATE(fmt, ...) \
> + do { printf("PSTATE: " fmt , ## __VA_ARGS__); } while (0)
> +#else
> +#define DPRINTF_PSTATE(fmt, ...) do {} while (0)
> +#endif
> +
> #ifdef TARGET_SPARC64
> #ifndef TARGET_ABI32
> #define AM_CHECK(env1) ((env1)->pstate & PS_AM)
> @@ -3244,6 +3252,12 @@ static inline uint64_t *get_gregset(uint64_t pstate)
> {
> switch (pstate) {
> default:
> + DPRINTF_PSTATE("ERROR in get_gregset: active pstate bits=%lX %s %s
> %s",
> + pstate,
> + (pstate&PS_IG)?"IG":"",
> + (pstate&PS_MG)?"MG":"",
> + (pstate&PS_AG)?"AG":"" );
> + /* pass through to normal set of global registers */
%lX format is not correct on 64 bit hosts and nobody uses upper case
hex, please use just %x. The spacing is too tight.
On UltraSPARC-IV and T1/2 the bits are interpreted differently (GL) so
the printout would be wrong, but that can be disregarded for now.
> case 0:
> return env->bgregs;
> case PS_AG:
> @@ -3269,12 +3283,18 @@ static inline void change_pstate(uint64_t new_pstate)
> new_pstate_regs = new_pstate & 0xc01;
>
> if (new_pstate_regs != pstate_regs) {
> + DPRINTF_PSTATE("change_pstate: switching regs old=%lX new=%lX\n",
> + pstate_regs, new_pstate_regs);
Same format issue here.
> // Switch global register bank
> src = get_gregset(new_pstate_regs);
> dst = get_gregset(pstate_regs);
> memcpy32(dst, env->gregs);
> memcpy32(env->gregs, src);
> }
> + else {
> + DPRINTF_PSTATE("change_pstate: regs new=%lX (unchanged)\n",
> + new_pstate_regs);
> + }
And here.
- [Qemu-devel] [PATCH 0/9] sparc64: tick timers, Igor V. Kovalenko, 2010/01/05
- [Qemu-devel] [PATCH 1/9] sparc64: trace pstate and global register set changes, Igor V. Kovalenko, 2010/01/05
- Re: [Qemu-devel] [PATCH 1/9] sparc64: trace pstate and global register set changes,
Blue Swirl <=
- [Qemu-devel] [PATCH 2/9] sparc64: add PSR and PIL to cpu state dump, Igor V. Kovalenko, 2010/01/05
- [Qemu-devel] [PATCH 3/9] sparc64: use helper_wrpil to check pending irq on write, Igor V. Kovalenko, 2010/01/05
- [Qemu-devel] [PATCH 4/9] sparc64: check for pending irq when pil, pstate or softint is changed, Igor V. Kovalenko, 2010/01/05
- [Qemu-devel] [PATCH 5/9] sparc64: add macros to deal with softint and timer interrupt, Igor V. Kovalenko, 2010/01/05
- [Qemu-devel] [PATCH 6/9] sparc64: clear exception_index with -1 value, Igor V. Kovalenko, 2010/01/05