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[Qemu-devel] [PATCH] mips: No MIPS16 support for 4Kc, 4KEc cores
From: |
Stefan Weil |
Subject: |
[Qemu-devel] [PATCH] mips: No MIPS16 support for 4Kc, 4KEc cores |
Date: |
Tue, 15 Dec 2009 14:03:03 +0100 |
Fix regression introduced by d19954f46dfc262612c30e9534e660e953049487.
4Kc and 4KEc don't support MIPS16.
Signed-off-by: Stefan Weil <address@hidden>
---
target-mips/translate_init.c | 6 +++---
1 files changed, 3 insertions(+), 3 deletions(-)
diff --git a/target-mips/translate_init.c b/target-mips/translate_init.c
index 11bc47c..b710979 100644
--- a/target-mips/translate_init.c
+++ b/target-mips/translate_init.c
@@ -105,7 +105,7 @@ static const mips_def_t mips_defs[] =
.CP0_Config1 = MIPS_CONFIG1 | (15 << CP0C1_MMU) |
(0 << CP0C1_IS) | (3 << CP0C1_IL) | (1 << CP0C1_IA) |
(0 << CP0C1_DS) | (3 << CP0C1_DL) | (1 << CP0C1_DA) |
- (1 << CP0C1_CA),
+ (0 << CP0C1_CA),
.CP0_Config2 = MIPS_CONFIG2,
.CP0_Config3 = MIPS_CONFIG3,
.CP0_LLAddr_rw_bitmask = 0,
@@ -147,7 +147,7 @@ static const mips_def_t mips_defs[] =
.CP0_Config1 = MIPS_CONFIG1 | (15 << CP0C1_MMU) |
(0 << CP0C1_IS) | (3 << CP0C1_IL) | (1 << CP0C1_IA) |
(0 << CP0C1_DS) | (3 << CP0C1_DL) | (1 << CP0C1_DA) |
- (1 << CP0C1_CA),
+ (0 << CP0C1_CA),
.CP0_Config2 = MIPS_CONFIG2,
.CP0_Config3 = MIPS_CONFIG3,
.CP0_LLAddr_rw_bitmask = 0,
@@ -188,7 +188,7 @@ static const mips_def_t mips_defs[] =
.CP0_Config1 = MIPS_CONFIG1 | (15 << CP0C1_MMU) |
(0 << CP0C1_IS) | (3 << CP0C1_IL) | (1 << CP0C1_IA) |
(0 << CP0C1_DS) | (3 << CP0C1_DL) | (1 << CP0C1_DA) |
- (1 << CP0C1_CA),
+ (0 << CP0C1_CA),
.CP0_Config2 = MIPS_CONFIG2,
.CP0_Config3 = MIPS_CONFIG3 | (0 << CP0C3_VInt),
.CP0_LLAddr_rw_bitmask = 0,
--
1.6.5
- [Qemu-devel] [PATCH] mips: No MIPS16 support for 4Kc, 4KEc cores,
Stefan Weil <=