[Qemu-devel] Re: irq latency and tcg

[Paul Brook]

> According to comment in exec-all.h:
> /* Deterministic execution requires that IO only be performed on the last
>    instruction of a TB so that interrupts take effect immediately.  */
> 
> Sparc generator must then violate this assumption. Is the assumption
> valid also when not using icount and should the check be enabled for
> all cases, not just icount?

Not really.  With -icount we're trying to achieve deterministic behavior[1]. 
When icount is disabled a few extra instructions interrupt latency is the 
least of your problems.

I guess with in-core peripherals you may be able to accurately predict 
interrupt response. However for the vast majority of cases I wouldn't be 
surprised if real hardware has a few cycles latency anyway.

Paul

[1] Even with -icount, qemu is still a long way from being cycle accurate. The 
goal is to give reproducible and consistent results. Actual realtime 
characteristics are still likely to be very different from real hardware.

Paul