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[Qemu-devel] [PATCH 09/11] gdbstub: add MIPS16 support
From: |
Nathan Froyd |
Subject: |
[Qemu-devel] [PATCH 09/11] gdbstub: add MIPS16 support |
Date: |
Tue, 8 Dec 2009 08:06:30 -0800 |
The only thing to do here is to expose the current processor mode to GDB
and to set the processor mode properly when we change the PC.
Signed-off-by: Nathan Froyd <address@hidden>
---
gdbstub.c | 18 +++++++++++++++---
1 files changed, 15 insertions(+), 3 deletions(-)
diff --git a/gdbstub.c b/gdbstub.c
index 5320b1c..6180171 100644
--- a/gdbstub.c
+++ b/gdbstub.c
@@ -1053,7 +1053,7 @@ static int cpu_gdb_read_register(CPUState *env, uint8_t
*mem_buf, int n)
case 34: GET_REGL(env->active_tc.HI[0]);
case 35: GET_REGL(env->CP0_BadVAddr);
case 36: GET_REGL((int32_t)env->CP0_Cause);
- case 37: GET_REGL(env->active_tc.PC);
+ case 37: GET_REGL(env->active_tc.PC | !!(env->hflags & MIPS_HFLAG_M16));
case 72: GET_REGL(0); /* fp */
case 89: GET_REGL((int32_t)env->CP0_PRid);
}
@@ -1114,7 +1114,14 @@ static int cpu_gdb_write_register(CPUState *env, uint8_t
*mem_buf, int n)
case 34: env->active_tc.HI[0] = tmp; break;
case 35: env->CP0_BadVAddr = tmp; break;
case 36: env->CP0_Cause = tmp; break;
- case 37: env->active_tc.PC = tmp; break;
+ case 37:
+ env->active_tc.PC = tmp & ~(target_ulong)1;
+ if (tmp & 1) {
+ env->hflags |= MIPS_HFLAG_M16;
+ } else {
+ env->hflags &= ~(MIPS_HFLAG_M16);
+ }
+ break;
case 72: /* fp, ignored */ break;
default:
if (n > 89)
@@ -1658,7 +1665,12 @@ static void gdb_set_cpu_pc(GDBState *s, target_ulong pc)
#elif defined (TARGET_SH4)
s->c_cpu->pc = pc;
#elif defined (TARGET_MIPS)
- s->c_cpu->active_tc.PC = pc;
+ s->c_cpu->active_tc.PC = pc & ~(target_ulong)1;
+ if (pc & 1) {
+ s->c_cpu->hflags |= MIPS_HFLAG_M16;
+ } else {
+ s->c_cpu->hflags &= ~(MIPS_HFLAG_M16);
+ }
#elif defined (TARGET_MICROBLAZE)
s->c_cpu->sregs[SR_PC] = pc;
#elif defined (TARGET_CRIS)
--
1.6.3.2
- [Qemu-devel] [PATCH v2 00/11] target-mips: add mips16 support, Nathan Froyd, 2009/12/08
- [Qemu-devel] [PATCH 11/11] target-mips: set Config1.CA for MIPS16-aware CPUs, Nathan Froyd, 2009/12/08
- [Qemu-devel] [PATCH 02/11] target-mips: change interrupt bits to be mips16-aware, Nathan Froyd, 2009/12/08
- [Qemu-devel] [PATCH 09/11] gdbstub: add MIPS16 support,
Nathan Froyd <=
- [Qemu-devel] [PATCH 01/11] target-mips: add new HFLAGs for JALX and 16/32-bit delay slots, Nathan Froyd, 2009/12/08
- [Qemu-devel] [PATCH 08/11] target-mips: add mips16 instruction decoding, Nathan Froyd, 2009/12/08
- [Qemu-devel] [PATCH 05/11] target-mips: add gen_base_offset_addr, Nathan Froyd, 2009/12/08
- [Qemu-devel] [PATCH 10/11] target-mips: add copyright notice for mips16 work, Nathan Froyd, 2009/12/08
- [Qemu-devel] [PATCH 04/11] target-mips: make gen_compute_branch 16/32-bit-aware, Nathan Froyd, 2009/12/08
- [Qemu-devel] [PATCH 03/11] target-mips: move ROTR and ROTRV inside gen_shift_{imm, }, Nathan Froyd, 2009/12/08
- [Qemu-devel] [PATCH 07/11] target-mips: add enums for MIPS16 opcodes, Nathan Froyd, 2009/12/08
- [Qemu-devel] [PATCH 06/11] target-mips: split out delay slot handling, Nathan Froyd, 2009/12/08