[Qemu-devel] [PATCH v2 00/11] target-mips: add mips16 support

[Nathan Froyd]

This patchset adds MIPS16 support to the MIPS backend.  MIPS16 is a
compact encoding of a subset of the MIPS integer instructions, similar
to ARM's Thumb mode.  Mode switching occurs when either a special
instruction (JALX) is executed, or when a jump-to-register instruction
is executed; the instruction mode for the target PC is indicated by the
low bit of the register.

The patches have been tested with GCC's testsuite and GDB's testsuite.

Changes from v1:
  Fixed bug preventing Linux boot
  Fixed usermode compilation error
  Fixed confusion of delay slot size vs. branch size
  Fixed bugs in PC-relative loads and adds
  Moved mode bit from ISAMode field to hflags
  Implemented extended I64 opcodes
  Implemented LDPC instruction
  Implemented DADDIUPC
  64-bit MIPS16 instructions cause RI exceptions when not running in 64-bit mode
    (This is required; see section 1.5 of MIPS16e 64-bit spec: MD00077.)
  Deleted MIPS16 ASE from TODO
  Flipped Config1.CA bit for appropriate CPUs

-Nathan