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[Qemu-devel] [PATCH 01/12] TCG "sync" op
From: |
Ulrich Hecht |
Subject: |
[Qemu-devel] [PATCH 01/12] TCG "sync" op |
Date: |
Wed, 21 Oct 2009 15:52:22 +0200 |
sync allows concurrent accesses to locations in memory through different TCG
variables. This comes in handy when you are emulating CPU registers that can
be used as either 32 or 64 bit, as TCG doesn't know anything about aliases.
See the s390x target for an example.
Fixed sync_i64 build failure on 32-bit targets.
Signed-off-by: Ulrich Hecht <address@hidden>
---
tcg/tcg-op.h | 12 ++++++++++++
tcg/tcg-opc.h | 2 ++
tcg/tcg.c | 6 ++++++
3 files changed, 20 insertions(+), 0 deletions(-)
diff --git a/tcg/tcg-op.h b/tcg/tcg-op.h
index faf2e8b..c1b4710 100644
--- a/tcg/tcg-op.h
+++ b/tcg/tcg-op.h
@@ -316,6 +316,18 @@ static inline void tcg_gen_br(int label)
tcg_gen_op1i(INDEX_op_br, label);
}
+static inline void tcg_gen_sync_i32(TCGv_i32 arg)
+{
+ tcg_gen_op1_i32(INDEX_op_sync_i32, arg);
+}
+
+#if TCG_TARGET_REG_BITS == 64
+static inline void tcg_gen_sync_i64(TCGv_i64 arg)
+{
+ tcg_gen_op1_i64(INDEX_op_sync_i64, arg);
+}
+#endif
+
static inline void tcg_gen_mov_i32(TCGv_i32 ret, TCGv_i32 arg)
{
if (!TCGV_EQUAL_I32(ret, arg))
diff --git a/tcg/tcg-opc.h b/tcg/tcg-opc.h
index b7f3fd7..5dcdeba 100644
--- a/tcg/tcg-opc.h
+++ b/tcg/tcg-opc.h
@@ -40,6 +40,7 @@ DEF2(call, 0, 1, 2, TCG_OPF_SIDE_EFFECTS) /* variable number
of parameters */
DEF2(jmp, 0, 1, 0, TCG_OPF_BB_END | TCG_OPF_SIDE_EFFECTS)
DEF2(br, 0, 0, 1, TCG_OPF_BB_END | TCG_OPF_SIDE_EFFECTS)
+DEF2(sync_i32, 0, 1, 0, 0)
DEF2(mov_i32, 1, 1, 0, 0)
DEF2(movi_i32, 1, 0, 1, 0)
/* load/store */
@@ -109,6 +110,7 @@ DEF2(neg_i32, 1, 1, 0, 0)
#endif
#if TCG_TARGET_REG_BITS == 64
+DEF2(sync_i64, 0, 1, 0, 0)
DEF2(mov_i64, 1, 1, 0, 0)
DEF2(movi_i64, 1, 0, 1, 0)
/* load/store */
diff --git a/tcg/tcg.c b/tcg/tcg.c
index 3c0e296..8eb60f8 100644
--- a/tcg/tcg.c
+++ b/tcg/tcg.c
@@ -1930,6 +1930,12 @@ static inline int tcg_gen_code_common(TCGContext *s,
uint8_t *gen_code_buf,
// dump_regs(s);
#endif
switch(opc) {
+ case INDEX_op_sync_i32:
+#if TCG_TARGET_REG_BITS == 64
+ case INDEX_op_sync_i64:
+#endif
+ temp_save(s, args[0], s->reserved_regs);
+ break;
case INDEX_op_mov_i32:
#if TCG_TARGET_REG_BITS == 64
case INDEX_op_mov_i64:
--
1.6.2.1
- [Qemu-devel] [PATCH 00/12] S/390 support, Ulrich Hecht, 2009/10/21
- [Qemu-devel] [PATCH 01/12] TCG "sync" op,
Ulrich Hecht <=
- [Qemu-devel] [PATCH 02/12] S/390 disassembler fixes, Ulrich Hecht, 2009/10/21
- [Qemu-devel] [PATCH 03/12] S/390 CPU emulation, Ulrich Hecht, 2009/10/21
- [Qemu-devel] [PATCH 04/12] S/390 host build system support, Ulrich Hecht, 2009/10/21
- [Qemu-devel] [PATCH 05/12] S/390 target build system support, Ulrich Hecht, 2009/10/21
- [Qemu-devel] [PATCH 06/12] S/390 host support for TCG, Ulrich Hecht, 2009/10/21
- [Qemu-devel] [PATCH 07/12] linux-user: S/390 64-bit (s390x) support, Ulrich Hecht, 2009/10/21
- [Qemu-devel] [PATCH 08/12] linux-user: don't do locking in single-threaded processes, Ulrich Hecht, 2009/10/21
- [Qemu-devel] [PATCH 09/12] linux-user: dup3, fallocate syscalls, Ulrich Hecht, 2009/10/21
- [Qemu-devel] [PATCH 10/12] linux-user: define a couple of syscalls for non-uid16 targets, Ulrich Hecht, 2009/10/21
- [Qemu-devel] [PATCH 11/12] linux-user: getpriority errno fix, Ulrich Hecht, 2009/10/21