[Qemu-devel] [PATCH 19/25] pci: use helper function in pci_default_write_config()

[Isaku Yamahata]

use helper function in pci_default_write_config() to
check whether the configuration space is changed.

Cc: Michael S. Tsirkin <address@hidden>
Signed-off-by: Isaku Yamahata <address@hidden>
---
 hw/pci.c |   18 +++++++++++-------
 hw/pci.h |    7 ++++++-
 2 files changed, 17 insertions(+), 8 deletions(-)

diff --git a/hw/pci.c b/hw/pci.c
index f697d9f..2054902 100644
--- a/hw/pci.c
+++ b/hw/pci.c
@@ -661,21 +661,25 @@ uint32_t pci_default_read_config(PCIDevice *d,
 
 void pci_default_write_config(PCIDevice *d, uint32_t addr, uint32_t val, int l)
 {
-    uint8_t orig[PCI_CONFIG_SPACE_SIZE];
     int i;
     uint32_t config_size = pcie_config_size(d);
+    uint8_t *orig = pci_write_config_init(d, addr, l);
 
-    /* not efficient, but simple */
-    memcpy(orig, d->config, PCI_CONFIG_SPACE_SIZE);
     for(i = 0; i < l && addr < config_size; val >>= 8, ++i, ++addr) {
         uint8_t wmask = d->wmask[addr];
         d->config[addr] = (d->config[addr] & ~wmask) | (val & wmask);
     }
-    if ((memcmp(orig + PCI_BASE_ADDRESS_0, d->config + PCI_BASE_ADDRESS_0, 24) 
||
-         memcmp(orig + PCI_ROM_ADDRESS, d->config + PCI_ROM_ADDRESS, 4))
-        || ((orig[PCI_COMMAND] ^ d->config[PCI_COMMAND])
-            & (PCI_COMMAND_MEMORY | PCI_COMMAND_IO)))
+
+    if (pci_config_changed(orig, d->config, addr, l,
+                           PCI_BASE_ADDRESS_0, PCI_BASE_ADDRESS_5 + 4) ||
+        pci_config_changed_with_size(orig, d->config, addr, l,
+                                     PCI_ROM_ADDRESS, 4) ||
+        pci_config_changed_with_size(orig, d->config, addr, l,
+                                     PCI_COMMAND, 1)) {
         pci_update_mappings(d);
+    }
+
+    pci_write_config_done(orig);
 }
 
 static void pci_data_write_common(PCIDevice *pci_dev,
diff --git a/hw/pci.h b/hw/pci.h
index ec989f0..f19b7a8 100644
--- a/hw/pci.h
+++ b/hw/pci.h
@@ -124,7 +124,12 @@ static inline int pci_bar_is_64bit(const PCIIORegion *r)
 #define  PCI_HEADER_TYPE_BRIDGE                1
 #define  PCI_HEADER_TYPE_CARDBUS       2
 #define  PCI_HEADER_TYPE_MULTI_FUNCTION 0x80
-#define PCI_BASE_ADDRESS_0     0x10    /* 32 bits */
+#define PCI_BASE_ADDRESS_0      0x10    /* 32 bits */
+#define PCI_BASE_ADDRESS_1      0x14    /* 32 bits [htype 0,1 only] */
+#define PCI_BASE_ADDRESS_2      0x18    /* 32 bits [htype 0 only] */
+#define PCI_BASE_ADDRESS_3      0x1c    /* 32 bits */
+#define PCI_BASE_ADDRESS_4      0x20    /* 32 bits */
+#define PCI_BASE_ADDRESS_5      0x24    /* 32 bits */
 #define PCI_PRIMARY_BUS                0x18    /* Primary bus number */
 #define PCI_SECONDARY_BUS      0x19    /* Secondary bus number */
 #define PCI_SEC_STATUS         0x1e    /* Secondary status register, only bit 
14 used */
-- 
1.6.0.2