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[Qemu-devel] [PATCH 05/16] Peripheral driver for S3C SOC clock control.
From: |
Vincent Sanders |
Subject: |
[Qemu-devel] [PATCH 05/16] Peripheral driver for S3C SOC clock control. |
Date: |
Sat, 23 May 2009 17:35:23 +0100 |
emulation of the S3c24xx SOC clock and power management controller
Signed-off-by: Vincent Sanders <address@hidden>
---
Makefile.target | 2 +-
hw/s3c2410x.c | 6 ++
hw/s3c2440.c | 6 ++
hw/s3c24xx.h | 6 ++
hw/s3c24xx_clkcon.c | 134 +++++++++++++++++++++++++++++++++++++++++++++++++++
5 files changed, 153 insertions(+), 1 deletions(-)
create mode 100644 hw/s3c24xx_clkcon.c
diff --git a/Makefile.target b/Makefile.target
index 1201cd3..d08bb36 100644
--- a/Makefile.target
+++ b/Makefile.target
@@ -648,7 +648,7 @@ OBJS+= omap_sx1.o palm.o tsc210x.o
OBJS+= nseries.o blizzard.o onenand.o vga.o cbus.o tusb6010.o usb-musb.o
OBJS+= mst_fpga.o mainstone.o
OBJS+= musicpal.o pflash_cfi02.o
-OBJS+= s3c24xx_memc.o s3c24xx_irq.o
+OBJS+= s3c24xx_memc.o s3c24xx_irq.o s3c24xx_clkcon.o
OBJS+= s3c2410x.o s3c2440.o
OBJS+= framebuffer.o
OBJS+= syborg.o syborg_fb.o syborg_interrupt.o syborg_keyboard.o
diff --git a/hw/s3c2410x.c b/hw/s3c2410x.c
index 987b14b..fe685e8 100644
--- a/hw/s3c2410x.c
+++ b/hw/s3c2410x.c
@@ -24,6 +24,9 @@
/* Interrupt controller */
#define CPU_S3C2410X_IRQ_BASE (CPU_S3C2410X_PERIPHERAL + 0xA000000)
+/* Clock control */
+#define CPU_S3C2410X_CLKCON_BASE (CPU_S3C2410X_PERIPHERAL + 0xC000000)
+
/* Initialise a Samsung S3C2410X SOC ARM core and internal peripherals. */
S3CState *
s3c2410x_init(int sdram_size)
@@ -51,5 +54,8 @@ s3c2410x_init(int sdram_size)
/* Interrupt controller */
s->irq = s3c24xx_irq_init(s, CPU_S3C2410X_IRQ_BASE);
+ /* Clock and power control */
+ s->clkcon = s3c24xx_clkcon_init(s, CPU_S3C2410X_CLKCON_BASE, 12000000);
+
return s;
}
diff --git a/hw/s3c2440.c b/hw/s3c2440.c
index 1f86c0f..b79451e 100644
--- a/hw/s3c2440.c
+++ b/hw/s3c2440.c
@@ -24,6 +24,9 @@
/* Interrupt controller */
#define CPU_S3C2440_IRQ_BASE (CPU_S3C2440_PERIPHERAL + 0xA000000)
+/* Clock control */
+#define CPU_S3C2440_CLKCON_BASE (CPU_S3C2440_PERIPHERAL + 0xC000000)
+
/* Initialise a Samsung S3C2440 SOC ARM core and internal peripherals. */
S3CState *
s3c2440_init(int sdram_size)
@@ -49,5 +52,8 @@ s3c2440_init(int sdram_size)
/* Interrupt controller */
s->irq = s3c24xx_irq_init(s, CPU_S3C2440_IRQ_BASE);
+ /* Clock and power control */
+ s->clkcon = s3c24xx_clkcon_init(s, CPU_S3C2440_CLKCON_BASE, 12000000);
+
return s;
}
diff --git a/hw/s3c24xx.h b/hw/s3c24xx.h
index 8233757..000c9ba 100644
--- a/hw/s3c24xx.h
+++ b/hw/s3c24xx.h
@@ -21,6 +21,9 @@ typedef struct S3CState_s {
/* IRQ controller state */
struct s3c24xx_irq_state_s *irq;
+ /* Clock and power control */
+ struct s3c24xx_clkcon_state_s *clkcon;
+
} S3CState;
@@ -33,5 +36,8 @@ struct s3c24xx_irq_state_s *s3c24xx_irq_init(S3CState *soc,
target_phys_addr_t b
/* get the qemu interrupt from an irq number */
qemu_irq s3c24xx_get_irq(struct s3c24xx_irq_state_s *s, int inum);
+/* initialise clock controller */
+struct s3c24xx_clkcon_state_s *s3c24xx_clkcon_init(S3CState *soc,
target_phys_addr_t base_addr, uint32_t ref_freq);
+
#endif /* S3C24XX_H */
diff --git a/hw/s3c24xx_clkcon.c b/hw/s3c24xx_clkcon.c
new file mode 100644
index 0000000..439ddbb
--- /dev/null
+++ b/hw/s3c24xx_clkcon.c
@@ -0,0 +1,134 @@
+/* hw/s3c24xx_clkcon.c
+ *
+ * Samsung S3C24XX Clock control emulation
+ *
+ * Copyright 2006, 2007, 2008 Daniel Silverstone and Vincent Sanders
+ *
+ * This file is under the terms of the GNU General Public
+ * License Version 2
+ */
+
+#include "hw.h"
+
+#include "s3c24xx.h"
+
+/* Lock time RW */
+#define S3C_REG_LOCKTIME 0
+
+/* MPLL Control RW */
+#define S3C_REG_MPLLCON 1
+
+/* UPLL Control RW */
+#define S3C_REG_UPLLCON 2
+
+/* Clock Generator Control RW */
+#define S3C_REG_CLKCON 3
+
+/* CLKCON IDLE */
+#define S3C_REG_CLKCON_IDLE (1<<2)
+
+/* Slow Clock Control RW */
+#define S3C_REG_CLKSLOW 4
+
+/* Clock divider control RW */
+#define S3C_REG_CLKDIVN 5
+
+/* Clock controller state */
+struct s3c24xx_clkcon_state_s {
+ CPUState *cpu_env;
+ uint32_t ref_freq; /* frequency of reference xtal or extclock */
+ uint32_t clkcon_reg[6];
+};
+
+static void
+s3c24xx_clkcon_write_f(void *opaque, target_phys_addr_t addr_, uint32_t value)
+{
+ struct s3c24xx_clkcon_state_s *s = (struct s3c24xx_clkcon_state_s *)opaque;
+ int addr = (addr_ & 0x1F) >> 2;
+ int idle_rising_edge = 0;
+
+ if (addr < 0 || addr > 5)
+ addr = 5;
+
+ if (addr == S3C_REG_CLKCON) {
+ if (!(s->clkcon_reg[addr] & S3C_REG_CLKCON_IDLE) &&
+ (value & S3C_REG_CLKCON_IDLE))
+ idle_rising_edge = 1;
+ }
+
+ s->clkcon_reg[addr] = value;
+
+ if (idle_rising_edge) {
+ cpu_interrupt(s->cpu_env, CPU_INTERRUPT_HALT);
+ }
+}
+
+static uint32_t
+s3c24xx_clkcon_read_f(void *opaque, target_phys_addr_t addr_)
+{
+ struct s3c24xx_clkcon_state_s *s = (struct s3c24xx_clkcon_state_s *)opaque;
+ int addr = (addr_ & 0x1F) >> 2;
+
+ if (addr < 0 || addr > 5)
+ addr = 5;
+
+ return s->clkcon_reg[addr];
+}
+
+static CPUReadMemoryFunc *s3c24xx_clkcon_read[] = {
+ &s3c24xx_clkcon_read_f,
+ &s3c24xx_clkcon_read_f,
+ &s3c24xx_clkcon_read_f,
+};
+
+static CPUWriteMemoryFunc *s3c24xx_clkcon_write[] = {
+ &s3c24xx_clkcon_write_f,
+ &s3c24xx_clkcon_write_f,
+ &s3c24xx_clkcon_write_f,
+};
+
+static void s3c24xx_clkcon_save(QEMUFile *f, void *opaque)
+{
+ struct s3c24xx_clkcon_state_s *s = (struct s3c24xx_clkcon_state_s *)opaque;
+ int i;
+
+ for (i = 0; i < 6; i ++)
+ qemu_put_be32s(f, &s->clkcon_reg[i]);
+}
+
+static int s3c24xx_clkcon_load(QEMUFile *f, void *opaque, int version_id)
+{
+ struct s3c24xx_clkcon_state_s *s = (struct s3c24xx_clkcon_state_s *)opaque;
+ int i;
+
+ for (i = 0; i < 6; i ++)
+ qemu_get_be32s(f, &s->clkcon_reg[i]);
+
+ return 0;
+}
+
+struct s3c24xx_clkcon_state_s *
+s3c24xx_clkcon_init(S3CState *soc, target_phys_addr_t base_addr, uint32_t
ref_freq)
+{
+ int tag;
+ struct s3c24xx_clkcon_state_s *s;
+
+ s = qemu_mallocz(sizeof(struct s3c24xx_clkcon_state_s));
+
+ tag = cpu_register_io_memory(0, s3c24xx_clkcon_read, s3c24xx_clkcon_write,
s);
+ cpu_register_physical_memory(base_addr, 6 * 4, tag);
+ register_savevm("s3c24xx_clkcon", 0, 0, s3c24xx_clkcon_save,
s3c24xx_clkcon_load, s);
+
+ s->cpu_env = soc->cpu_env;
+ s->ref_freq = ref_freq;
+
+ /* initialise register values to power on defaults */
+ s->clkcon_reg[S3C_REG_LOCKTIME] = 0x00FFFFFF;
+ s->clkcon_reg[S3C_REG_MPLLCON] = 0x0005C080;
+ s->clkcon_reg[S3C_REG_UPLLCON] = 0x00028080;
+ s->clkcon_reg[S3C_REG_CLKCON] = 0x0007FFF0;
+ s->clkcon_reg[S3C_REG_CLKSLOW] = 0x00000004;
+ s->clkcon_reg[S3C_REG_CLKDIVN] = 0x00000000;
+
+ return s;
+}
--
1.6.0.4
- [Qemu-devel] Add ARM S3C SOC core, drivers and boards - v3, Vincent Sanders, 2009/05/23
- [Qemu-devel] [PATCH 01/16] Add ARM 920T CPU identifier, Vincent Sanders, 2009/05/23
- [Qemu-devel] [PATCH 02/16] S3C2410 and S3C2440 core SOC implementation., Vincent Sanders, 2009/05/23
- [Qemu-devel] [PATCH 04/16] Peripheral driver for S3C SOC IRQ controller., Vincent Sanders, 2009/05/23
- [Qemu-devel] [PATCH 03/16] Peripheral driver for S3C SOC SDRAM controller., Vincent Sanders, 2009/05/23
- [Qemu-devel] [PATCH 15/16] Add SMDK2410 board support, Vincent Sanders, 2009/05/23
- [Qemu-devel] [PATCH 13/16] Peripheral driver for S3C OHCI controller, Vincent Sanders, 2009/05/23
- [Qemu-devel] [PATCH 05/16] Peripheral driver for S3C SOC clock control.,
Vincent Sanders <=
- [Qemu-devel] [PATCH 14/16] Add bast board support, Vincent Sanders, 2009/05/23
- [Qemu-devel] [PATCH 08/16] Peripheral driver for S3C SOC real time clock., Vincent Sanders, 2009/05/23
- [Qemu-devel] [PATCH 11/16] Peripheral driver for S3C SOC LCD controller, Vincent Sanders, 2009/05/23
- [Qemu-devel] [PATCH 09/16] Peripheral driver for S3C SOC general purpose I/O, Vincent Sanders, 2009/05/23
- [Qemu-devel] [PATCH 12/16] Peripheral driver for S3C SOC NAND controller, Vincent Sanders, 2009/05/23
- [Qemu-devel] [PATCH 10/16] Peripheral driver for S3C SOC I2C controller., Vincent Sanders, 2009/05/23
- [Qemu-devel] [PATCH 07/16] Peripheral driver for S3C SOC Serial ports., Vincent Sanders, 2009/05/23
- [Qemu-devel] [PATCH 06/16] Peripheral driver for S3C SOC timers., Vincent Sanders, 2009/05/23